AD566A

FEATURESSingle Chip ConstructionVery High-Speed Settling to 1/2 LSBAD565A: 250 ns maxAD566A: 350 ns maxFull-Scale Switching Time: 30 nsGuaranteed for Operation with ؎12 V Supplies:AD565A with –12 V Supply: AD566ALinearity Guaranteed Over Temperature:1/2 LSB max (K, T Grades)Monotonicity Guaranteed Over TemperatureLow Power:AD566A = 180 mW max;AD565A = 225 mW maxUse with On-Board High-Stability Reference (AD565A)or with External Reference (AD566A)Low CostMlL-STD-883-Compliant Versions AvailablePRODUCT DESCRIPTIONThe AD565A and AD566A are fast 12-bit digital-to-analogconverters that incorporate the latest advances in analog circuitdesign to achieve high speeds at low cost.The AD565A and AD566A use 12 precision, high-speed bipolarcurrent-steering switches, control amplifier and a laser-trimmedthin-film resistor network to produce a very fast, high accuracyanalog output current. The AD565A also includes a buriedZener reference that features low-noise, long-term stability andtemperature drift characteristics comparable to the best discretereference diodes.The combination of performance and flexibility in the AD565Aand AD566A has resulted from major innovations in circuitdesign, an important new high-speed bipolar process, and con-tinuing advances in laser-wafer-trimming techniques (LWT).The AD565A and AD566A have a 10–90% full-scale transitiontime less than 35 ns and settle to within ±1/2 LSB in 250 nsmax (350 ns for AD566A). Both are laser-trimmed at the waferlevel to ±1/8 LSB typical linearity and are specified to ±1/4 LSBmax error (K and T grades) at +25°C. High speed and accuracymake the AD565A and AD566A the ideal choice for high-speeddisplay drivers as well as fast analog-to-digital converters.The laser trimming process which provides the excellent linear-ity is also used to trim both the absolute value and the tempera-ture coefficient of the reference of the AD565A resulting in atypical full-scale gain TC of 10 ppm/°C. When tighter TC per-formance is required or when a system reference is available, theAD566A may be used with an external reference.*Covered by Patent Nos.: 3,803,590; RE 28,633; 4,213,806; 4,136,349;4,020,486; 3,747,088.REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

High Speed 12-BitMonolithic D/A ConvertersAD565A*/AD566A*FUNCTIONAL BLOCK DIAGRAMSREF OUTVCCBIPOLAR OFF20V SPAN10VAD565A5k⍀REF19.95k⍀0.5mA9.95k⍀10V SPANINIREF5k⍀DAC OUTREF20k⍀IDACOUT =I4 ؋ IO8k⍀GNDREF ؋ CODECODE INPUT–VEEPOWERMSBLSBGNDBIPOLAR OFFAD566A20V SPAN9.95k⍀5k⍀REF19.95k⍀0.5mA10V SPANINI5k⍀REFIDACDAC OUTREF20k⍀OUT =4 ؋ IIGNDREF ؋ CODEO8k⍀CODE INPUT–VEEPOWERMSBLSBGNDAD565A and AD566A are available in four performancegrades. The J and K are specified for use over the 0°C to +70°Ctemperature range while the S and T grades are specified for the–55°C to +125°C range. The D grades are all packaged in a24-lead, hermetically sealed, ceramic, dual-in-line package. TheJR grade is packaged in a 28-lead plastic SOIC.PRODUCT HIGHLIGHTS1. The wide output compliance range of the AD565A andAD566A are ideally suited for fast, low noise, accurate volt-age output configurations without an output amplifier.2. The devices incorporate a newly developed, fully differential,nonsaturating precision current switching cell structurewhich combines the dc accuracy and stability first developedin the AD562/3 with very fast switching times and anoptimally-damped settling characteristic.3. The devices also contain SiCr thin film application resistorswhich can be used with an external op amp to provide aprecision voltage output or as input resistors for a successiveapproximation A/D converter. The resistors are matched tothe internal ladder network to guarantee a low gain tempera-ture coefficient and are laser-trimmed for minimumfull-scale and bipolar offset errors.4. The AD565A and AD566A are available in versions compli-ant with MIL-STD-883. Refer to the Analog Devices Mili-tary Products Databook or current /883B data sheet fordetailed specifications.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: http://www.analog.comFax: 781/326-8703© Analog Devices, Inc., 2000

AD565A–SPECIFICATIONS(T = +25؇C, V = +15 V, V = +15 V, unless otherwise noted.)

A

CC

EE

ModelDATA INPUTS1 (Pins 13 to 24)TTL or 5 Volt CMOSInput VoltageBit ON Logic “1”Bit OFF Logic “0”Logic Current (Each Bit)Bit ON Logic “1”Bit OFF Logic “0”RESOLUTIONOUTPUTCurrentUnipolar (All Bits On)Bipolar (All Bits On or Off)Resistance (Exclusive of Span Resistors)OffsetUnipolarBipolar (Figure 3, R2 = 50 Ω Fixed)CapacitanceCompliance VoltageTMIN to TMAXACCURACY (Error Relative toFull Scale) +25°CTMIN to TMAXDIFFERENTIAL NONLINEARITY+25°CTMIN to TMAXTEMPERATURE COEFFICIENTSWith Internal ReferenceUnipolar ZeroBipolar ZeroGain (Full Scale)Differential NonlinearitySETTLING TIME TO 1/2 LSBAll Bits ON-to-OFF or OFF-to-ONFULL-SCALE TRANSITION10% to 90% Delay plus Rise Time90% to 10% Delay plus Fall TimeTEMPERATURE RANGEOperatingStoragePOWER REQUIREMENTSVCC, +11.4 to +16.5 V deVEE, –11.4 to –16.5 V dcPOWER SUPPLY GAIN SENSITIVITY2VCC = +11.4 to +16.5 V dcVEE = –11.4 to –16.5 V dcPROGRAMMABLE OUTPUT RANGES (See Figures 2, 3, 4)MinAD565AJTypMaxMinAD565AKTypMaxUnits+2.0+120+35+5.5+0.8+300+10012–2.4؎1.2100.050.15+10±1/4(0.006)±1/2(0.012)؎1/2(0.012)؎3/4(0.018)+2.0+120+35+5.5+0.8+300+10012–2.4؎1.2100.050.1+10±1/8(0.003)±1/4(0.006)؎1/4(0.006)؎1/2(0.012)VVµAµABitsmAmAkΩ% of F.S. Range% of F.S. RangepFVLSB% of F.S. RangeLSB% of F.S. RangeLSB–1.6؎0.86–2.0±1.080.010.0525–1.6؎0.86–2.0±1.080.010.0525–1.5–1.5±1/2؎3/4MONOTONICITY GUARANTEED1515225015300–653–123150 to +5–2.5 to +2.50 to +10–5 to +5–10 to +10±0.1±0.25±0.15159.901.5±0.05؎0.25؎0.15210504003050+70+1505–181025±1/4؎1/2MONOTONICITY GUARANTEED1510225015300–653–123150 to +5–2.5 to +2.50 to +10–5 to +5–10 to +10±0.1±0.25±0.15159.901.5±0.05؎0.25±0.1210204003050+70+1505–181025ppm/°Cppm/°Cppm/°Cppm/°Cnsnsns°C°CmAmAppm of F.S./%ppm of F.S./%VVVVV% of F.S. Range% of F.S. Range% of F.S. Range% of F.S. RangekΩVmAmWEXTERNAL ADJUSTMENTSGain Error with Fixed 50 ΩResistor for R2 (Figure 2)Bipolar Zero Error with Fixed50 Ω Resistor for R1 (Figure 3)Gain Adjustment Range (Figure 2)Bipolar Zero Adjustment RangeREFERENCE INPUTInput ImpedanceREFERENCE OUTPUTVoltageCurrent (Available for External Loads)3POWER DISSIPATION2010.002.52252510.103452010.002.52252510.10345NOTES1The digital inputs are guaranteed but not tested over the operating temperature range.2The power supply gain sensitivity is tested in reference to a VCC, VEE of ±15 V dc.3For operation at elevated temperatures the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.Specifications subject to change without notice.–2–REV. D

AD565A/AD566A

ModelDATA INPUTS1 (Pins 13 to 24)TTL or 5 Volt CMOSInput VoltageBit ON Logic “1”Bit OFF Logic “0”Logic Current (Each Bit)Bit ON Logic “1”Bit OFF Logic “0”RESOLUTIONOUTPUTCurrentUnipolar (All Bits On)Bipolar (All Bits On or Off)Resistance (Exclusive of Span Resistors)OffsetUnipolarBipolar (Figure 3, R2 = 50 Ω Fixed)CapacitanceCompliance VoltageTMIN to TMAXACCURACY (Error Relative toFull Scale) +25°CTMIN to TMAXDIFFERENTIAL NONLINEARITY+25°CTMIN to TMAXTEMPERATURE COEFFICIENTSWith Internal ReferenceUnipolar ZeroBipolar ZeroGain (Full Scale)Differential NonlinearitySETTLING TIME TO 1/2 LSBAll Bits ON-to-OFF or OFF-to-ONFULL-SCALE TRANSITION10% to 90% Delay plus Rise Time90% to 10% Delay plus Fall TimeTEMPERATURE RANGEOperatingStoragePOWER REQUIREMENTSVCC, +11.4 to +16.5 V dcVEE, –11.4 to –16.5 V dcPOWER SUPPLY GAIN SENSITIVITY2VCC = +11.4 to +16.5 V dcVEE = –11.4 to –16.5 V dcPROGRAMMABLE OUTPUT RANGES(See Figures 2, 3, 4)MinAD565ASTypMaxMinAD565ATTypMaxUnits+2.0+120+35+5.5+0.8+300+10012–2.4؎1.2100.050.15+10±1/4(0.006)±1/2(0.012)؎1/2(0.012)؎3/4(0.018)+2.0+120+35+5.5+0.8+300+10012–2.4؎1.2100.050.1+10±1/8(0.003)±1/4(0.006)؎1/4(0.006)؎1/2(0.012)VVµAµABitsmAmAkΩ% of F.S. Range% of F.S. RangepFVLSB% of F.S. RangeLSB% of F.S. RangeLSB–1.6؎0.86–2.0±1.080.010.0525–1.6؎0.86–2.0±1.080.010.0525–1.5–1.5±1/2؎3/4MONOTONICITY GUARANTEED151522501530–55–653–123150 to +5–2.5 to +2.50 to +10–5 to +5–10 to +10±0.1±0.25±0.15159.901.5±0.05؎0.25؎0.15210304003050+125+1505–181025±1/4؎1/2MONOTONICITY GUARANTEED151022501530–55–653–123150 to +5–2.5 to +2.50 to +10–5 to +5–10 to +10±0.1±0.25±0.15159.901.5±0.05؎0.25؎0.12101003050+125+1505–181025ppm/°Cppm/°Cppm/°Cppm/°Cnsnsns°C°CmAmAppm of F.S./%ppm of F.S./%VVVVV% of F.S. Range% of F.S. Range% of F.S. Range% of F.S. RangekΩVmAmWEXTERNAL ADJUSTMENTSGain Error with Fixed 50 ΩResistor for R2 (Figure 2)Bipolar Zero Error with Fixed50 Ω Resistor for R1 (Figure 3)Gain Adjustment Range (Figure 2)Bipolar Zero Adjustment RangeREFERENCE INPUTInput ImpedanceREFERENCE OUTPUTVoltageCurrent (Available for External Loads)3POWER DISSIPATION2010.002.52252510.103452010.002.52252510.10345Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minand max specifications are guaranteed, although only those shown in boldface are tested on all production units.Specification subject to change without notice.REV. D–3–

AD566A–SPECIFICATIONS(T = +25؇C, V = –15 V, unless otherwise noted)

A

EE

ModelDATA INPUTS1 (Pins 13 to 24)TTL or 5 Volt CMOSInput VoltageBit ON Logic “1”Bit OFF Logic “0”Logic Current (Each Bit)Bit ON Logic “1”Bit OFF Logic “0”RESOLUTIONOUTPUTCurrentUnipolar (All Bits On)Bipolar (All Bits On or Off)Resistance (Exclusive of Span Resistors)OffsetUnipolar (Adjustable to Zero per Figure 3)Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)CapacitanceCompliance VoltageTMIN to TMAXACCURACY (Error Relative toFull Scale) +25°CTMIN to TMAXDIFFERENTIAL NONLINEARITY+25°CTMIN to TMAXTEMPERATURE COEFFICIENTSUnipolar ZeroBipolar ZeroGain (Full Scale)Differential NonlinearitySETTLING TIME TO 1/2 LSBAll Bits ON-to-OFF or OFF-to-ON (Figure 8)FULL-SCALE TRANSITION10% to 90% Delay plus Rise Time90% to 10% Delay plus Fall TimePOWER REQUIREMENTSVEE, –11.4 to –16.5 V dcPOWER SUPPLY GAIN SENSITIVITY2VEE = –11.4 to –16.5 V dcPROGRAMMABLE OUTPUT RANGES (see Figures 3, 4, 5)MinAD566AJTypMaxMinAD566AKTypMaxUnits+2.00+120+35+5.5+0.8+300+10012–2.4؎1.2100.050.15+10±1/4(0.006)±1/2(0.012)؎1/2(0.012)؎3/4(0.018)+2.00+120+35+5.5+0.8+300+10012–2.4؎1.2100.050.1+10±1/8(0.003)±1/4(0.006)؎1/4(0.006)؎1/2(0.012)VVµAµABitsmAmAkΩ% of F.S. Range% of F.S. RangepFVLSB% of F.S. RangeLSB% of F.S. RangeLSBppm/°Cppm/°Cppm/°Cppm/°CnsnsnsmAppm of F.S./%VVVVV–1.6؎0.86–2.0±1.080.010.0525–1.6؎0.86–2.0±1.080.010.0525–1.5–1.5±1/2؎3/4MONOTONICITY GUARANTEED15722501530–12150 to +5–2.5 to +2.50 to +10–5 to +5–10 to +10±0.1±0.25±0.1515±0.05؎0.25؎0.15210103503050–1825±1/4؎1/2MONOTONICITY GUARANTEED15322501530–12150 to +5–2.5 to +2.50 to +10–5 to +5–10 to +10±0.1±0.25±0.1515±0.05؎0.25؎0.121053503050–1825EXTERNAL ADJUSTMENTSGain Error with Fixed 50 ΩResistor for R2 (Figure 3)Bipolar Zero Error with Fixed50 Ω Resistor for R1 (Figure 4)Gain Adjustment Range (Figure 3)Bipolar Zero Adjustment RangeREFERENCE INPUTInput ImpedancePOWER DISSIPATIONMULTIPLYING MODE PERFORMANCE (All Models)QuadrantsReference VoltageAccuracyReference Feedthrough (Unipolar Mode,All Bits OFF, and 1 V to +10 V [p-p], Sine WaveFrequency for 1/2 LSB [p-p] Feedthrough)Output Slew Rate 10%–90%90%–10%Output Settling Time (All Bits ON and a 0 V–10 VStep Change in Reference Voltage)CONTROL AMPLIFIERFull Power BandwidthSmall-Signal Closed-Loop Bandwidth% of F.S. Range% of F.S. Range% of F.S. Range% of F.S. RangekΩmW20180253002018025300Two (2): Bipolar Operation at Digital Input Only+1 V to +10 V, Unipolar10 Bits (±0.05% of Reduced F.S.) for 1 V dc Reference Voltage40 kHz typ5 mA/µs1 mA/µs1.5 µs to 0.01% F.S.300 kHz1.8 MHzNOTES1The digital input levels are guaranteed but not tested over the temperature range.2The power supply gain sensitivity is tested in reference to a VEE of –1.5 V dc.Specifications subject to change without notice.–4–REV. D

AD565A/AD566A

ModelDATA INPUTS1 (Pins 13 to 24)TTL or 5 Volt CMOSInput VoltageBit ON Logic “1”Bit OFF Logic “0”Logic Current (Each Bit)Bit ON Logic “1”Bit OFF Logic “0”RESOLUTIONOUTPUTCurrentUnipolar (All Bits On)Bipolar (All Bits On or Off)Resistance (Exclusive of Span Resistors)OffsetUnipolar (Adjustable to Zero per Figure 3)Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)CapacitanceCompliance VoltageTMIN to TMAXACCURACY (Error Relative toFull Scale) +25°CTMIN to TMAXDIFFERENTIAL NONLINEARITY+25°CTMIN to TMAXTEMPERATURE COEFFICIENTSUnipolar ZeroBipolar ZeroGain (Full Scale)Differential NonlinearitySETTLING TIME TO 1/2 LSBAll Bits ON-to-OFF or OFF-to-ON (Figure 8)FULL-SCALE TRANSITION10% to 90% Delay plus Rise Time90% to 10% Delay plus Fall TimePOWER REQUIREMENTSVEE, –11.4 to –16.5 V dcPOWER SUPPLY GAIN SENSITIVITY2VEE = –11.4 to –16.5 V dcPROGRAMMABLE OUTPUT RANGES(see Figures 3, 4, 5)MinAD566ASTypMaxMinAD566ATTypMaxUnits+2.00+120+35+5.5+0.8+300+10012–2.4؎1.2100.050.15+10±1/4(0.006)±1/2(0.012)؎1/2(0.012)؎3/4(0.018)+2.00+120+35+5.5+0.8+300+10012–2.4؎1.2100.050.1+10±1/8(0.003)±1/4(0.006)؎1/4(0.006)؎1/2(0.012)VVµAµABitsmAmAkΩ% of F.S. Range% of F.S. RangepFVLSB% of F.S. RangeLSB% of F.S. RangeLSBppm/°Cppm/°Cppm/°Cppm/°CnsnsnsmAppm of F.S./%VVVVV–1.6؎0.86–2.0±1.080.010.0525–1.6؎0.86–2.0±1.080.010.0525–1.5–1.5±1/2؎3/4MONOTONICITY GUARANTEED15722501530–12150 to +5–2.5 to +2.50 to +10–5 to +5–10 to +10±0.1±0.25±0.1515±0.05؎0.25؎0.15210103503050–1825±1/4؎1/2MONOTONICITY GUARANTEED15322501530–12150 to +5–2.5 to +2.50 to +10–5 to +5–10 to +10±0.1±0.25±0.1515±0.05؎0.25؎0.121053503050–1825EXTERNAL ADJUSTMENTSGain Error with Fixed 50 ΩResistor for R2 (Figure 3)Bipolar Zero Error with Fixed50 Ω Resistor for R1 (Figure 4)Gain Adjustment Range (Figure 3)Bipolar Zero Adjustment RangeREFERENCE INPUTInput ImpedancePOWER DISSIPATIONMULTIPLYING MODE PERFORMANCE (All Models)QuadrantsReference VoltageAccuracyReference Feedthrough (Unipolar Mode,All Bits OFF, and 1 V to +10 V [p-p], Sine WaveFrequency for l/2 LSB [p-p] Feedthrough)Output Slew Rate 10%–90%90%–10%Output Settling Time (All Bits ON and a 0 V–10 VStep Change in Reference Voltage)CONTROL AMPLIFIERFull Power BandwidthSmall-Signal Closed-Loop Bandwidth% of F.S. Range% of F.S. Range% of F.S. Range% of F.S. RangekΩmW20180253002018025300Two (2): Bipolar Operation at Digital Input Only+1 V to +10 V, Unipolar10 Bits (±0.05% of Reduced F.S.) for 1 V dc Reference Voltage40 kHz typ5 mA/µs1 mA/µs1.5 µs to 0.01% F.S.300 kHz1.8 MHzNOTESSpecifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and maxspecifications are guaranteed, although only those shown in boldface are tested on all production units.Specification subject to change without notice.REV. D

–5–

AD565A/AD566A

ABSOLUTE MAXIMUM RATINGSGROUNDING RULESVCC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 VVEE to Power Ground (AD565A) . . . . . . . . . . . . 0 V to –18 VVoltage on DAC Output (Pin 9) . . . . . . . . . . . . –3 V to +12 VDigital Inputs (Pins 13 to 24) toPower Ground . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 VREF IN to Reference Ground . . . . . . . . . . . . . . . . . . . . ±12 VBipolar Offset to Reference Ground . . . . . . . . . . . . . . . ±12 V10 V Span R to Reference Ground . . . . . . . . . . . . . . . . ±12 V20 V Span R to Reference Ground . . . . . . . . . . . . . . . . ±24 VREF OUT (AD565A) . . . . . Indefinite Short to Power GroundMomentary Short to VCCPower Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mWAD565A ORDERING GUIDEMax GainT.C. (ppm of F.S./؇C)5050203015TemperatureRange0°C to +70°C0°C to +70°C0°C to +70°C–55°C to +125°C–55°C to +125°CLinearityError MaxPackage@ +25؇COptions2±1/2 LSB±1/2 LSB±1/4 LSB±1/2 LSB±1/4 LSBCeramic (D-24)SOIC (R-28)Ceramic (D-24)Ceramic (D-24)Ceramic (D-24)The AD565A and AD566A bring out separate reference andpower grounds to allow optimum connections for low noise andhigh-speed performance. These grounds should be tied togetherat one point, usually the device power ground. The separateground returns are provided to minimize current flow inlow-level signal paths. In this way, logic return currents are notsummed into the same return path with analog signals.CONNECTING THE AD565A FOR BUFFERED VOLTAGEOUTPUTModel1AD565AJDAD565AJRAD565AKDAD565ASDAD565ATD1NOTESFor details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current/883B data sheet.2D = Ceramic DIP, R = SOIC.The standard current-to-voltage conversion connections usingan operational amplifier are shown here with the preferredtrimming techniques. If a low offset operational amplifier(AD510L, AD517L, AD741L, AD301AL, AD OP07) is used,excellent performance can be obtained in many situations with-out trimming (an op amp with less than 0.5 mV max offsetvoltage should be used to keep offset errors below 1/2 LSB). Ifa 50Ω fixed resistor is substituted for the 100Ω trimmer, uni-polar zero will typically be within ±1/2 LSB (plus op amp off-set), and full-scale accuracy will be within 0.1% (0.25% max).Substituting a 50Ω resistor for the 100Ω bipolar offset trimmerwill give a bipolar zero error typically within ±2 LSB (0.05%).The AD509 is recommended for buffered voltage-output appli-cations which require a settling time to ±1/2 LSB of one micro-second. The feedback capacitor is shown with the optimumvalue for each application; this capacitor is required to compen-sate for the 25 picofarad DAC output capacitance.AD566A ORDERING GUIDEMax GainT.C. (ppm of F.S./؇C)103103TemperatureRange0°C to +70°C0°C to +70°C–55°C to +125°C–55°C to +125°CLinearityError MaxPackage@ +25؇COption2±1/2 LSB±1/4 LSB±1/2 LSB±1/4 LSBCeramic (D-24)Ceramic (D-24)Ceramic (D-24)Ceramic (D-24)Model1AD566AJDAD566AKDAD566ASDAD566ATDNOTES1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current/883B data sheet.2D = Ceramic DIP.–6–REV. D

AD565A/AD566A

PIN DESIGNATIONS24-Lead DIPNC1NC2VCC3REF OUT (+10V ±1%)4REF GND5REF IN624232221BIT 1 IN (MSB)BIT 2 INBIT 3 INBIT 4 INBIT 5 INNC1NC2REF GND3AMP SUMMING JUNCTION4REF V HI IN5–VEE –15V IN (20mA)BIPOLAR OFFSET IN

NC

DAC OUT (–2mA F.S.)

624232221BIT 1 IN (MSB)BIT 2 INBIT 3 INBIT 4 INBIT 5 INTOP VIEW19BIT 6 IN(Not to Scale)18BIT 7 IN–VEE71716151413AD565A20TOP VIEW19BIT 6 IN

7(Not to Scale)18BIT 7 IN1716151413AD566A20BIPOLAR OFFSET IN8DAC OUT (–2mA F.S.)

9BIT 8 INBIT 9 INBIT 10 INBIT 11 INBIT 12 IN (LSB)BIT 8 INBIT 9 INBIT 10 INBIT 11 INBIT 12 IN (LSB)10V SPAN R1020V SPAN R11PWR GND1210V SPAN R1020V SPAN R11PWR GND12NC = NO CONNECTNC = NO CONNECT28-Lead SOICNC1NCNC

232827262524NCBIT 1 (MSB)BIT 2BIT 3BIT 4BIT 5VCC4REF OUT (10V)

REF GNDREF IN

NC–VEE

567AD565A23TOP VIEW22BIT 6(Not to Scale)821BIT 79201918171615BIT 8BIT 9BIT 10BIT 11BIT 12 (LSB)PWR GNDBIPOLAR OFFSET IN10DAC OUT11NC1210V SPAN R1320V SPAN R14NC = NO CONNECTREV. D–7–

AD565A/AD566A

FIGURE 1. UNIPOLAR CONFIGURATIONSTEP I . . . OFFSET ADJUSTThis configuration will provide a unipolar 0 volt to +10 voltoutput range. In this mode, the bipolar terminal, Pin 8, shouldbe grounded if not used for trimming.+15V100k⍀100⍀REFOUTVCCBIPOLAR OFF20V SPANR2100⍀10V9.95k⍀5k⍀5k⍀10pFIO8k⍀IOUT =4 ؋ IREF ؋ CODECODEINPUTMSBLSBDACOUTAD5092.4k⍀OUTPUT0V TO+10V10V SPANR150k⍀–15VTurn OFF all bits. Adjust 100Ω trimmer R1 to give –5.000volts output.STEP II . . . GAIN ADJUSTTurn ON All bits. Adjust 100Ω gain trimmer R2 to give a read-ing of +4.9976 volts.Please note that it is not necessary to trim the op amp to obtainfull accuracy at room temperature. In most bipolar situations,an op amp trim is unnecessary unless the untrimmed offset driftof the op amp is excessive.FIGURE 3. OTHER VOLTAGE RANGESAD565A0.5mAIREF19.95k⍀REFINREFGND20k⍀DACPOWERGND–VEEFigure 1. 0 V to +10 V Unipolar Voltage OutputSTEP I . . . ZERO ADJUSTThe AD565A can also be easily configured for a unipolar 0 voltto +5 volt range or ±2.5 volt and ±10 volt bipolar ranges byusing the additional 5k application resistor provided at the 20volt span R terminal, Pin 11. For a 5 volt span (0 to +5 or±2.5), the two 5k resistors are used in parallel by shorting Pin11 to Pin 9 and connecting Pin 10 to the op amp output and thebipolar offset either to ground for unipolar or to REF OUT forthe bipolar offset either to ground for unipolar or to REF OUTfor the bipolar range. For the ±10 volt range (20 volt span) usethe 5k resistors in series by connecting only Pin 11 to the opamp output and the bipolar offset connected as shown. The ±10volt option is shown in Figure 3.Turn all bits OFF and adjust zero trimmer R1, until the outputreads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim isnot needed, but Pin 8 should then be connected to Pin 12.STEP II . . . GAIN ADJUSTREFOUTVCCR1100⍀BIPOLAR OFF20V SPANTurn all bits ON and adjust 100Ω gain trimmer R2, until theoutput is 9.9976 volts. (Full scale is adjusted to 1LSB less thannominal full scale of 10.000 volts.) If a 10.2375V full scale isdesired (exactly 2.5mV/bit), insert a 120Ω resistor in serieswith the gain resistor at Pin 10 to the op amp output.FIGURE 2.BIPOLAR CONFIGURATIONR2100⍀10V9.95k⍀5k⍀5k⍀10V SPAN10pFAD565A0.5mAIREF19.95k⍀REFINREFGND20k⍀IO8k⍀IOUT =4 ؋ IREF ؋ CODECODEINPUTDACOUTAD5093.0k⍀OUTPUT–10V TO+10VDACThis configuration will provide a bipolar output voltage from–5.000 to +4.9976 volts, with positive full scale occurring withall bits ON (all 1s).POWERGND–VEEMSBLSBFigure 3.±10 V Voltage OutputREFOUTVCCR1100⍀BIPOLAR OFF20V SPANR2100⍀10V9.95k⍀5k⍀5k⍀10pFIO8k⍀IOUT =4 ؋ IREF ؋ CODECODEINPUTMSBLSBDACOUTAD5092.4k⍀OUTPUT–5V TO+5V10V SPANAD565A0.5mAIREF19.95k⍀REFINREFGND20k⍀DACPOWERGND–VEEFigure 2.±5 V Bipolar Voltage Output–8–REV. D

AD565A/AD566A

CONNECTING THE AD566A FOR BUFFERED VOLTAGEOUTPUTFIGURE 5.BIPOLAR CONFIGURATIONThe standard current-to-voltage conversion connections usingan operational amplifier are shown here with the preferred trim-ming techniques. If a low offset operational amplifier (AD510L,AD517L, AD741L, AD301AL, AD OP07) is used, excellentperformance can be obtained in many situations without trim-ming (an op amp with less than 0.5 mV max offset voltageshould be used to keep offset errors below 1/2 LSB). If a 50Ωfixed resistor is substituted for the 100Ω trimmer, unipolar zerowill typically be within ±1/2 LSB (plus op amp offset), and fullscale accuracy will be within 0.1% (0.25% max). Substituting a50Ω resistor for the 100Ω bipolar offset trimmer will give abipolar zero error typically within ±2 LSB (0.05%).The AD509 is recommended for buffered voltage-output appli-cations which require a settling time to ±1/2LSB of one micro-second. The feedback capacitor is shown with the optimumvalue for each application; this capacitor is required to compen-sate for the 25 picofarad DAC output capacitance.FIGURE 4. UNIPOLAR CONFIGURATIONThis configuration will provide a bipolar output voltage from–5.000 volts to +4.9976 volts, with positive full scale occurringwith all bits ON (all 1s).R1100⍀BIPOLAR OFF20V SPAN9.95k⍀5k⍀5k⍀AD566A10V SPANR2100⍀REFIN19.95k⍀10pF0.5mAIREFIO8k⍀IOUT =4 ؋ IREF ؋ CODECODEINPUTMSBLSBDACOUTAD5092.4k⍀+V10VEREFAD561REFGNDDAC20k⍀POWERGND–VEEThis configuration will provide a unipolar 0 volt to +10 voltoutput range. In this mode, the bipolar terminal, Pin 7, shouldbe grounded if not used for trimming.+15V100⍀100k⍀BIPOLAR OFFR150k⍀–15V20V SPAN9.95k⍀5k⍀5k⍀R2100⍀+V10VFigure 5.±5 V Bipolar Voltage OutputSTEP I . . . OFFSET ADJUSTTurn OFF all bits. Adjust 100Ω trimmer R1 to give –5.000output volts.STEP II . . . GAIN ADJUSTAD566ATurn ON all bits. Adjust 100Ω gain trimmer R2 to give a read-ing of +4.9976 volts.Please note that it is not necessary to trim the op amp to obtainfull accuracy at room temperature. In most bipolar situations,an op amp trim is unnecessary unless the untrimmed offset driftof the op amp is excessive.10V SPANREFIN19.95k⍀EREFAD561REFGNDPOWERGND–VEE10pF0.5mAIREFIO8k⍀IOUT =4 ؋ IREF ؋ CODECODEINPUTMSBLSBDACOUTAD5092.4k⍀DAC20k⍀Figure 4.0 V to +10 V Unipolar Voltage OutputSTEP I . . . ZERO ADJUSTTurn all bits OFF and adjust zero trimmer, R1, until the outputreads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim isnot needed, but Pin 7 should then be connected to Pin 12.STEP II . . . GAIN ADJUSTTurn all bits ON and adjust 100Ω gain trimmer, R2, until theoutput is 9.9976 volts. (Full scale is adjusted to 1 LSB less thannominal full scale of 10.000 volts.) If a 10.2375 V full scale isdesired (exactly 2.5 mV/bit), insert a 120Ω resistor in serieswith the gain resistor at Pin 10 to the op amp output.REV. D–9–

AD565A/AD566A

FIGURE 6.OTHER VOLTAGE RANGESTable I.Digital Input CodesDIGITAL INPUTMSBLSBStraight BinaryZeroMid Scale – 1 LSB+1/2 FS+FS – l LSBANALOG OUTPUTOffset Binary–FSZero – 1 LSBZero+ FS – 1 LSBTwos Compl.*Zero+FS – 1 LSB–FSZero – 1 LSBThe AD566A can also be easily configured for a unipolar 0 voltto +5 volt range or ±2.5 volt and ±10 volt bipolar ranges byusing the additional 5k application resistor provided at the 20volt span R terminal, Pin 11. For a 5 volt span (0 V to +5 V or±2.5V), the two 5k resistors are used in parallel by shorting Pin11 to Pin 9 and connecting Pin 10 to the op amp output and thebipolar offset resistor either to ground for unipolar or to VREFfor the bipolar range. For the ±10 volt range (20 volt span) use0 0 0 0 0 0 0 0 0 0 0 00 1 1 1 1 1 1 1 1 1 1 11 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1 1 1 1*Inverts the MSB of the offset binary code with an external inverter to obtainthe 5k resistors in series by connecting only Pin 11 to the optwos complement.amp output and the bipolar offset connected as shown. The±10 volt option is shown in Figure 6.R15k⍀BIPOLAR OFFAD566A20V SPAN9.95k⍀14k⍀5k⍀10V SPAN10pFR25k⍀5k⍀REFIN19.95k⍀0.5mAIO8k⍀DACOUTI–V7.5VEREFDACAD561REFAD50920k⍀IOUT =4 ؋ IREF2.4k⍀REF ؋ CODEGNDPOWERCODEINPUTR3GND26k⍀*–VEEMSBLSB*THE PARALLEL COMBINATION OF THE BIPOLAR OFFSET RESISTORAND R3 ESTABLISHES A CURRENT TO BALANCE THE MSB CURRENT.THE EFFECT OF TEMPERATURE COEFFICIENT MISMATCH BETWEENTHE BIPOLAR RESISTOR COMBINATION AND DAC RESISTORS ISEXPANDED ON PREVIOUS PAGE.Fgure 6.±10 V Voltage Output–10–REV. D

AD565A/AD566A

OUTLINE DIMENSIONSDimensions shown in inches and (mm).Ceramic DIP (D-24)0.005 (0.13) MIN240.098 (2.49) MAX13REV. D0.610 (15.49)0.500 (12.70)112PIN 1 1.290 (32.77) MAX0.075 (1.91)0.620 (15.75)0.225 (5.72)0.015 (0.38)0.590 (14.99)MAX0.1500.200 (5.08)(3.81)0.015 (0.38)0.120 (3.05)MIN0.008 (0.20)0.023 (0.58)0.100 (2.)0.070 (1.78)SEATING0.014 (0.36)BSC0.030 (0.76)PLANESOIC (R-28) Package0.7125 (18.10)0.6969 (17.70)2815))))05.6.40.6.00(7(7 (10(10 92143.29.29193711400.4.3900PIN 10.1043 (2.65)0.0291 (0.74)0.0926 (2.35)0.0098 (0.25)x 45°8°0.0500 (1.27)0.0118 (0.30)0.05000.0192 (0.49)0.0040 (0.10)(1.27)BSC0.0138 (0.35)SEATINGPLANE0.0125 (0.32)0°0.0157 (0.40)0.0091 (0.23)–11–

)D .ver( 00/3–0–a4181C.A.S.U NI DETNIRPThis datasheet has been downloaded from:

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