Tester, parallel scan paths, and comparators in sa

专利名称：Tester, parallel scan paths, and comparators

in same functional circuits

发明人：Lee D. Whetsel申请号：US15243294申请日：20160822公开号：US09535127B2公开日：20170103

专利附图：

摘要：An integrated circuit includes combinational logic with flip-flops, parallel scanpaths with a scan input for receiving test stimulus data to be applied to the combinationallogic, combinational connections with the combinational logic for applying stimulus data

to the combinational logic and receiving response data from the combinational logic, ascan output for transmitting test response data obtained from the combinational logic,and control inputs having an enable input and a select input for operating the parallelscan paths, each scan path includes flip-flops of the combinational logic that, in a testmode, are connected in series, compare circuitry indicates the result of a comparison ofthe received test response data and the expected data at a fail flag output, and one ofthe scan paths includes a scan cell having an input coupled to the fail flag output.

申请人：TEXAS INSTRUMENTS INCORPORATED

地址：Dallas TX US

国籍：US

代理人：Lawrence J. Bassuk,Charles A. Brill,Frank D. Cimino

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