W3EG72126MS100D3MF资料

White Electronic DesignsW3EG72126S-D3

-JD3-AJD3PRELIMINARY*

1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL

FEATURES

󰀂 Double-data-rate architecture󰀂 DDR200, DDR266 and DDR333:

• JEDEC design specifi cations󰀂 Bi-directional data strobes (DQS)󰀂 Differential clock inputs (CK & CK#) 󰀂 Programmable Read Latency 2,2.5 (clock)󰀂 Programmable Burst Length (2,4,8)

󰀂 Programmable Burst type (sequential & interleave) 󰀂 Edge aligned data output, center aligned data input. 󰀂 Auto and self refresh 󰀂 Serial presence detect

󰀂 Power supply: VCC = 2.5V ± 0.20V󰀂 JEDEC standard 184 pin DIMM package

• Package height options:

JD3: 30.48mm (1.20\") and AJD3: 28.70mm (1.13\")

• Consult factory for availability of lead-free products.

DESCRIPTION

The W3EG72126S is a 128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eighteen 128Mx4 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

* This product is under development, is not qualifi ed or characterized and is subject to change without notice.

OPERATING FREQUENCIES

DDR333 @CL=2.5

Clock SpeedCL-tRCD-tRP

166MHz2.5-3-3

DDR266 @CL=2

133MHz2-2-2

DDR266 @CL=2

133MHz2-3-3

DDR266 @CL=2.5

133MHz2.5-3-3

DDR200 @CL=2

100MHz2-2-2

November 2004Rev. 3

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White Electronic DesignsW3EG72126S-D3

-JD3-AJD3PRELIMINARY

PIN CONFIGURATION

PIN1234567101112131415161718192021222324252627282930313233343536373839404142434446

SYMBOLVREFDQ0VSSDQ1DQS0DQ2VCCDQ3NCRESET#VSSDQ8DQ9DQS1VCCQNCNCVSSDQ10DQ11CKE0VCCQDQ16DQ17DQS2VSSA9DQ18A7VCCQDQ19A5DQ24VSSDQ25DQS3A4VCCDQ26DQ27A2VSSA1CB0CB1VCC

PIN474849505152535556575859606162636566676869707172737475767778798081828384858687809192

SYMBOLDQS8A0CB2VSSCB3BA1DQ32VCCQDQ33DQS4DQ34VSSBA0DQ35DQ40VCCQWE#DQ41CAS#VSSDQS5DQ42DQ43VCCNCDQ48DQ49VSSNCNCVCCQDQS6DQ50DQ51VSSVCCIDDQ56DQ57VCCDQS7DQ58DQ59VSSNCSDASCL

PIN939495969799100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138

SYMBOLVSSDQ4DQ5VCCQDQS9DQ6DQ7VSSNCNCNCVCCQDQ12DQ13DQS10VCCDQ14DQ15NCVCCQNCDQ20A12VSSDQ21A11DQS11VCCDQ22A8DQ23VSSA6DQ28DQ29VCCQDQS12A3DQ30VSSDQ31CB4CB5VCCQCK0CK0#

PIN13914014114214314414514614714814915015115215311551561571581591601611621631165166167168169170171172173174175176177178179180181182183184

SYMBOLVSSDQS17A10CB6VCCQCB7VSSDQ36DQ37VCCDQS13DQ38DQ39VSSDQ44RAS#DQ45VCCQCS0#NCDQS14VSSDQ46DQ47NCVCCQDQ52DQ53NCVCCDQS15DQDQ55VCCQNCDQ60DQ61VSSDQS16DQ62DQ63VCCQSA0SA1SA2VCCSPD

A0-A12BA0-BA1DQ0-DQ63CB0-CB7DQS0-DQS17CK0CK0#CKE0CS0#RAS#CAS#WE#VCCVCCQVSSVREFVCCSPDSDASCLSA0-SA2VCCIDNC

RESET#

PIN NAMES

Address input (Multiplexed)Bank Select AddressData Input/OutputCheck bits

Data Strobe Input/OutputClock InputClock Input

Clock Enable inputChip Select InputRow Address StrobeColumn Address StrobeWrite EnablePower Supply

Power Supply for DQSGround

Power Supply for ReferenceSerial EEPROM Power SupplySerial data I/OSerial clock

Address in EEPROMVCC Indentifi cation FlagNo ConnectReset Enable

November 2004Rev. 3

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White Electronic DesignsFUNCTIONAL BLOCK DIAGRAM

VSSRCS0#DQS0DQ0DQ1DQ2DQ3DQSI/O 3I/O 2I/O 1I/O 0CS#DMDQ4DQ5DQ6DQ7W3EG72126S-D3

-JD3-AJD3PRELIMINARY

DQS9DQSI/O 3I/O 2I/O 1I/O 0CS#DMDQS1DQ8DQ9DQ10DQ11DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0CS#DMDQS10DQ12DQ13DQ14DQ15DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0CS#DMDQS2CS#DMDQ16DQ17DQ18DQ19DQS11CS#DMDQ20DQ21DQ22DQ23DQS3DQS12CS#DMCS#DMDQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31CKO SDRAMPLLCS#DMDQS4DQ32DQ33DQ34DQ35DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0CS#DMDQS13DQ36DQ37DQ38DQ39DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0CKO#REGISTERDQS5DQ40DQ41DQ42DQ43DQS14CS#DMCS#DMDQ44DQ45DQ46DQ47Serial PDSCLDQS6CS#DMDQ48DQ49DQ50DQ51DQS15CS#DMDQ52DQ53DQDQ55WPSDAA0A1A2SA2SA0SA1DQS7DQ56DQ57DQ58DQ59DQSI/O 3I/O 2I/O 1I/O 0DQSI/O 3I/O 2I/O 1I/O 0CS#DMDQS16CS#DMDQ60DQ61DQ62DQ63VCCSPDVCC/VCCQVREFVSSSPDDDR SDRAMsDDR SDRAMsDDR SDRAMsDQS8CS#DMCB0CB1CB2CB3DQS17CB4CB5CB6CB7CS#DMCS0#BA0-BA1RAS#A0-A12CAS#CKE0WE#PCKPCK#REGISTERRCS0#RBA0 - RBA1RA0 - RA12RRAS#RCAS#RCKE0RWE#RESET#BA0 - BA1: DDR SDRAMsA0 - A12: DDR SDRAMsRAS#: DDR SDRAMsCAS#: DDR SDRAMsCKE: DDR SDRAMsWE: DDR SDRAMsNOTE: All resistor values are 22 ohms unless otherwise specifi edNotes:1. DQ-to-I/O wiring is shown as recommended but may be changed.2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.November 2004Rev. 3

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White Electronic DesignsABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to VSSVoltage on VCC supply relative to VSSStorage TemperaturePower DissipationShort Circuit Current

Note:

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

SymbolVIN, VOUTVCC, VCCQTSTGPDIOS

Value-0.5 to 3.6-1.0 to 3.6-55 to +150

2750

UnitsVV°C WmA

Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC CHARACTERISTICS

0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V

ParameterSupply VoltageSupply VoltageReference VoltageTermination VoltageInput High VoltageInput Low VoltageOutput High VoltageOutput Low Voltage

SymbolVCCVCCQVREFVTTVIHVILVOHVOL

Min2.32.31.151.15VREF + 0.15-0.3VTT + 0.76—

Max2.72.71.351.35VCCQ + 0.3VREF -0.15—VTT-0.76

UnitVVVVVVVV

CAPACITANCE

TA = 25°C. f = 1MHz, VCC = 2.5V ± 0.2V

Parameter

Input Capacitance (A0-A12)Input Capacitance (RAS#,CAS#,WE#)Input Capacitance (CKE0)Input Capacitance (CK0#,CK0)Input Capacitance (CS0#)Input Capacitance (DQM0-DQM8)Input Capacitance (BA0-BA1)

Data input/output capacitance (DQ0-DQ63)(DQS)Data input/output capacitance (CB0-CB7)

SymbolCIN1CIN2CIN3CIN4CIN5CIN6CIN7COUTCOUT

Max6.256.256.255.56.2586.2588

UnitpFpFpFpFpFpFpFpFpF

November 2004Rev. 3

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White Electronic DesignsIDD SPECIFICATIONS AND TEST CONDITIONS

0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V

Includes DDR SDRAM component only

ParameterOperating Current

SymbolIDD0

Conditions

One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles.

One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle.

All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low)CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM.

One device bank active; Power-Down mode; tCK (MIN); CKE=(low)CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle.Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.

Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle.tRC = tRC (MIN)CKE ≤ 0.2V

Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands.

DDR333@CL=2.5

Max

2340

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

DDR266@CL=2, 2.5

Max

2340

DDR200@CL=2

Max

2340

UnitsmA

Operating CurrentIDD1288028802880mA

Precharge Power-Down Standby Current

Idle Standby Current

IDD2P909090rnA

IDD2F810810810mA

Active Power-Down Standby Current Active Standby Current

IDD3P IDD3N

630900

630900

630900

mAmA

Operating CurrentIDD4R297029702970mA

Operating CurrentIDD4W315027902790rnA

Auto Refresh Current

Self Refresh CurrentOperating Current

IDD5IDD6IDD7A

5220907290

5220907200

5220907200

mAmAmA

November 2004Rev. 3

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White Electronic DesignsIDD SPECIFICATIONS AND TEST CONDITIONS

0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V

Includes PLL and register power

ParameterOperating Current

SymbolIDD0

Conditions

One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles.

One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle.

All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low)CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM.

One device bank active; Power-Down mode; tCK (MIN); CKE=(low)CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle.Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.

Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle.tRC = tRC (MIN)CKE ≤ 0.2V

Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands.

DDR333@CL=2.5

Max

2615

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

DDR266@CL=2, 2.5

Max

2615

DDR200@CL=2

Max

2615

UnitsmA

Operating CurrentIDD1315531553155mA

Precharge Power-Down Standby Current

Idle Standby Current

IDD2P909090rnA

IDD2F112011201120mA

Active Power-Down Standby Current Active Standby Current

IDD3P IDD3N

6301210

6301210

6301210

mAmA

Operating CurrentIDD4R324532453245mA

Operating CurrentIDD4W342530653065rnA

Auto Refresh Current

Self Refresh CurrentOperating Current

IDD5IDD6IDD7A

55304007565

55304007475

55304007475

mAmAmA

November 2004Rev. 3

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White Electronic DesignsDETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A

IDD1 : OPERATING CURRENT : ONE BANK

1. Typical Case : VCC=2.5V, T=25°C2. Worst Case : VCC=2.7V, T=10°C

3. Only one bank is accessed with tRC (min), Burst

Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA4. Timing Patterns :

•

DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,

BL=4, tRCD=2*tCK, tRAS=5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2.5) : tCK=7.5ns,

CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCKRead : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address

changing; 50% of data changing at every burstDDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address

changing; 50% of data changing at every burstDDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address

changing; 50% of data changing at every burst

•

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

IDD7A : OPERATING CURRENT : FOUR BANKS

1. Typical Case : VCC=2.5V, T=25°C2. Worst Case : VCC=2.7V, T=10°C

3. Four banks are being interleaved with tRC (min),

Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA4. Timing Patterns :

•

DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,

BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst

DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCKRead with Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst

DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst

DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst

•

•

•

•

•

Legend:

A = Activate, R = Read, W = Write, P = Precharge, N = NOPA (0-3) = Activate Bank 0-3R (0-3) = Read Bank 0-3

November 2004Rev. 3

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White Electronic DesignsW3EG72126S-D3

-JD3-AJD3PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS

0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V

AC CharacteristicsParameter

Access window of DQs from CK, CK#CK high-level widthCK low-level widthClock cycle time

DQ and DM input hold time relative to DQSDQ and DM input setup time relative to DQSDQ and DM input pulse width (for each input)Access window of DQS from CK, CK#DQS input high pulse widthDQS input low pulse width

DQS-DQ skew, DQS to last DQ valid, per group, per access

Write command to fi rst DQS latching transitionDQS falling edge to CK rising - setup timeDQS falling edge from CK rising - hold timeHalf clock period

Data-out high-impedance window from CK, CK#Data-out low-impedance window from CK, CK#Address and control input hold time (fast slew rate)Address and control input set-up time (fast slew rate)Address and control input hold time (slow slew rate)Address and control input setup time (slow slew rate)Address and control input pulse width (for each input)LOAD MODE REGISTER command cycle timeDQ-DQS hold, DQS to fi rst DQ to go non-valid, per access

Data hold skew factor

ACTIVE to PRECHARGE command

ACTIVE to READ with Auto precharge commandACTIVE to ACTIVE/AUTO REFRESH command periodAUTO REFRESH command period

CL=2.5CL=2

SymboltACtCHtCLtCK (2.5)tCK (2)tDHtDStDIPWtDQSCKtDQSHtDQSLtDQSQtDQSStDSStDSHtHPtHZtLZtIHftISftIHstISstIPWtMRDtQHtQHStRAStRAPtRCtRFC

42156072-0.70.750.750.80.82.212 tHP-tQHS

0.55 70,000

40156075

0.750.20.2tCH, tCL

+0.7

-0.750.900.90112.215tHP-tQHS

0.75120,000

40156075

0.450.451.75-0.60.350.35

0.451.25

0.750.20.2tCH, tCL

+0.75

-0.750.900.90112.215tHP-tQHS

0.75120,000

40156075

+0.6

Min-0.70.450.456335

Max+0.70.550.5513

Min-0.750.450.457.57.50.50.51.75-0.750.350.35

0.51.25

0.750.20.2tCH, tCL

+0.75

-0.750.900.90112.215 tHP-tQHS

0.75120,000

+0.75262

Max+0.750.550.551313

263/265Min-0.750.450.457.57.50.50.51.75-0.750.350.35

0.51.25

0.750.20.2tCH, tCL

+0.75

+0.75Max+0.750.550.551313

Min-0.750.450.457.57.50.50.51.75-0.750.350.35

0.51.25+0.75202

Max+0.750.550.551313

UnitsnstCKtCKnsnsnsnsnsnstCKtCKnstCKtCKtCKnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

211513,14188,198,20666613,141616222214,1714,1717Notes

November 2004Rev. 3

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White Electronic DesignsW3EG72126S-D3

-JD3-AJD3PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS (continued)

0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V

AC CharacteristicsParameter

ACTIVE to READ or WRITE delayPRECHARGE command periodDQS read preambleDQS read postamble

ACTIVE bank a to ACTIVE bank b commandDQS write preamble

DQS write preamble setup timeDQS write postambleWrite recovery time

Internal WRITE to READ command delayData valid output window

REFRESH to REFRESH command intervalAverage periodic refresh intervalTerminating voltage delay to VCC

Exit SELF REFRESH to non-READ commandExit SELF REFRESH to READ command

SymboltRCDtRPtRPREtRPSTtRRDtWPREtWPREStWPSTtWRtWTRNAtREFCtREFItVTDtXSNRtXSRD

075200Min15150.90.4120.2500.4151tQH-tDQSQ

70.37.8

075200

0.61.10.6335

Max

Min15150.90.4150.2500.4151tQH-tDQSQ

70.37.8

075200

0.61.10.6262

Max

263/265Min15150.90.4150.2500.4151tQH-tDQSQ

70.37.8

075200

0.61.10.6Max

Min15150.90.4150.2500.4151tQH-tDQSQ

70.37.80.61.10.6202

Max

UnitsnsnstCKtCKnstCKnstCKnstCK nsμsμsnsnstCK

13121210,11919Notes

November 2004Rev. 3

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White Electronic DesignsE

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

Notes

1.

All voltages referenced to VSS

2. Tests for AC timing, IDD, and electrical AC and DC characteristics

may be conducted at normal reference / supply voltage levels, but the related specifi cations and device operations are guaranteed for the full voltage range specifi ed.3.

Outputs are measured with equivalent load:

11. It is recommended that DQS be valid (HIGH or LOW) on or before

the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS.12. The refresh period is ms. This equates to an average refresh

rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed.13. The valid data window is derived by achieving other specifi cations

- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.14. Referenced to each output group: x4 = DQS with DQ0-DQ3.15. RADs and WRITEs with auto precharge are not allowed to be

issued until tRAS (MIN) can be satisfi ed prior to the internal precharge command being issued.16. JEDEC specifi es CK and CK# input slew rate must be > 1V/ns (2V/ns differentially).17. DQ and DM input slew rates must not deviate from DQS by more

than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain.18. tHP min is the lesser of tCL min and tCH min actually applied to the

device CK and CK# inputs, collectively during bank active.19. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX)

condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition.20. For slew rates greater than 1V/ns the (LZ) transition will start about

310ps earlier.21. CKE must be active (High) during the entire time a refresh

command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfi ed.22. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands).

VTTOutput(VOUT) 4.

AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).The AC and DC input level specifi cations are defi ned in the SSTL_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level).

For slew rates less than 1V/ns and greater than or equal to 0.5V/ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 335, slew rates must be greater than or equal to 0.5V/ns.

Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW.

50ΩReference Point30pF5.

6.

7.

8. tHZ and tLZ transitions occur in the same access time windows as

valid data transitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ).9.

The intent of the “Don’t Care” state after completion of the

postamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below VIHDC) prior to tDQSH (MIN).

10. This is not a device limit. The device will operate with a negative

value, but system performance could be degraded due to bus turnaround.

November 2004Rev. 3

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White Electronic DesignsORDERING INFORMATION FOR JD3

Part NumberW3EG72126S335JD3W3EG72126S262JD3W3EG72126S263JD3W3EG72126S265JD3W3EG72126S202JD3

Speed166MHz/333Mb/s133MHz/266Mb/s133MHz/266Mb/s133MHz/266Mb/s100MHz/200Mb/s

CAS Latency

2.5222.52

tRCD32332

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

tRP32332

Height*30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")

Note: Consult factory for availability of lead-free products. (F = Lead-Free, G = RoHS compliant)Vendor Code: M = Micron, S = Samsung

PACKAGE DIMENSIONS FOR JD3

133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))30.48(1.20 MAX)3.99(0.157)(MIN)3.81(0.150 MAX)17.78(0.700)10.01(0.394)6.35(0.250).77(2.550)1.27(0.050 TYP.)6.35(0.250)1.78(0.070)49.53(1.950)2.31(0.091)(2x)3.00(0.118)(4x)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

November 2004Rev. 3

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White Electronic DesignsORDERING INFORMATION FOR AJD3

Part Number

W3EG72126S335AJD3W3EG72126S262AJD3W3EG72126S263AJD3W3EG72126S265AJD3W3EG72126S202AJD3

Speed166MHz/333Mb/s133MHz/266Mb/s133MHz/266Mb/s133MHz/266Mb/s100MHz/200Mb/s

CAS Latency

2.5222.52

tRCD32332

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

tRP32332

Height*28.70 (1.13\")28.70 (1.13\")28.70 (1.13\")28.70 (1.13\")28.70 (1.13\")

Note: Consult factory for availability of lead-free products. (F = Lead-Free, G = RoHS compliant)Vendor Code: M = Micron, S = Samsung

PACKAGE DIMENSIONS FOR AJD3

133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))28.70(1.13 MAX)3.99(0.157)(MIN)3.81(0.150 MAX)17.78(0.700)10.01(0.394)6.35(0.250).77(2.550)1.27(0.050 TYP.)6.35(0.250)1.78(0.070)49.53(1.950)2.31(0.091)(2x)3.00(0.118)(4x)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

November 2004Rev. 3

12White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

元器件交易网www.cecb2b.com

White Electronic DesignsORDERING INFORMATION FOR D3

Part NumberW3EG72126S335D3W3EG72126S262D3W3EG72126S263D3W3EG72126S265D3W3EG72126S202D3

Speed166MHz/333Mb/s133MHz/266Mb/s133MHz/266Mb/s133MHz/266Mb/s100MHz/200Mb/s

CAS Latency

2.5222.52

tRCD32332

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

tRP32332

Height*28.58 (1.125\")28.58 (1.125\")28.58 (1.125\")28.58 (1.125\")28.58 (1.125\")

Note: Consult factory for availability of lead-free products. (F = Lead-Free, G = RoHS compliant)Vendor Code: M = Micron, S = Samsung

PACKAGE DIMENSIONS FOR D3

Not recommended for new designs133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))17.78(0.700)10.01(0.394)NNovember 2004Rev. 3

OCER TO6.35(0.250).77(2.550)6.35(0.250)1.78(0.070)13

MM49.53(1.950)DNE28.58(1.125 MAX)2.31(0.091)(2x)3.00(0.118)(4x)DE3.99(0.157)(MIN)3.81(0.150 MAX)1.27(0.050 TYP.)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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White Electronic DesignsPART NUMBERING GUIDE

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

W 3 E G 72 126M S xxx D3 x F/G

WEDCSDRAMDDRGOLDBUS WIDTHDEPTH:256 = 256Mb

2.5V

SPEED (MHz):166, 133, 100MHZ

PACKAGE:JD3, AJD3

COMPONENT VENDOR:M = Micron, S = SamsungF = LEAD-FREE,

G = RoHS COMPLIANT

November 2004Rev. 3

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White Electronic DesignsDocument Title

1GB - 128Mx72, DDR SDRAM Registered Module

W3EG72126S-D3

-JD3-AJD3PRELIMINARY

Revision HistoryRev #

Rev 0Rev 1Rev 2

History

Initial ReleaseAdded 333MHz Speed

Corrected Incidentals (abbreviations, / &

—

to #, symbols, etc.)

Release Date

3-18-021-30-033-3-04

Status

AdvancedAdvancedPreliminary

2.1 Corrected pages 1, 2, 4, 5, 6, 8, 9, 10

2.2 Corrected page 7 : Spec Items and Test Conditions2.3 Added JD3 and AJD3 package options

2.4 Added \"Not recommended for New Designs\" to D32.5 Added document title page2.6 Removed \"ED\" for Part Marking

Rev 3

3.1 Added Lead-Free and RoHS note3.2 Added vendor code options

M = MicronS = Samsung

November 2004

Preliminary

November 2004Rev. 3

15White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com