4K x 8 DUAL-PORTSTATIC RAM
Integrated Device Technology, Inc.IDT7134SA/LA
FEATURES:
•High-speed access
—Military: 25/35/45/55/70ns (max.)
—Commercial: 20/25/35/45/55/70ns (max.)•Low-power operation—IDT7134SA
Active: 500mW (typ.)Standby: 5mW (typ.)—IDT7134LA
Active: 500mW (typ.)Standby: 1mW (typ.)
•Fully asynchronous operation from either port•Battery backup operation—2V data retention•TTL-compatible; single 5V (±10%) power supply
•Available in several popular hermetic and plastic packages•Military product compliant to MIL-STD-883, Class B
•Industrial temperature range (–40°C to +85°C) is available,tested to military electrical specifications
DESCRIPTION:
The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAMdesigned to be used in systems where on-chip hardware portarbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed tobe able to externally arbitrate or withstand contention whenboth sides simultaneously access the same Dual-Port RAMlocation.
The IDT7134 provides two independent ports with separatecontrol, address, and I/O pins that permit independent,asynchronous access for reads or writes to any location inmemory. It is the user’s responsibility to ensure data integritywhen simultaneously accessing the same memory locationfrom both ports. An automatic power down feature, controlledby CE, permits the on-chip circuitry of each port to enter a verylow standby power mode.
Fabricated using IDT’s CMOS high-performancetechnology, these Dual-Port typically on only 500mW ofpower. Low-power (LA) versions offer battery backup dataretention capability, with each port typically consuming 200µWfrom a 2V battery.
The IDT7134 is packaged on either a sidebraze or plastic48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin CeramicFlatpack. Military grade product is manufactured in compliancewith the latest revision of MIL-STD-883, Class B, making itideally suited to military temperature applications demandingthe highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
R/WLCELOELI/O0L- I/O7LCOLUMNI/OCOLUMNI/OR/WRCEROERI/O0R- I/O7RA0L- A11LLEFT SIDEADDRESSDECODELOGICMEMORYARRAYRIGHT SIDEADDRESSDECODELOGICA0R- A11R2720 drw 01The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2720/4
6.041
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS(1,2)
N/CR/WLCELR/WRI/O4LI/O5LN/CGNDI/O0RI/O1RI/O2RI/O4RI/O5R2720 drw 02I/O3RI/O6RI/O6LI/O7LCELR/WLA11LA10LOELA0LA1LA2LA3LA4LA5LA6LA7LA8LA9LI/O0LI/O1LI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LGNDN/CA11R1482473443742841IDT713494010P48–139&1138C48–21237DIP13361435TOP15VIEW (3)34163317321831193020292128222723262425VCCCERR/WRA11RA10ROERA0RA1RA2RA3RA4RA5RA6RA7RA8RA9RI/O7RI/O6RI/O5RI/O4RI/O3RI/O2RI/O1RI/O0RINDEXA1LA2LA3LA4LA5LA6LA7LA8LA9LI/O0LI/O1LI/O2LI/O3L10111213141516171876321525150494847A10R444342414039383736A10LA11LA0LOELVCCCEROERA0RA1RA2RA3RA4RA5RA6RA7RA8RA9RN/CI/O7RIDT7134J52-1PLCCTOP VIEW (3)19353420212223242526272829303132332720 drw 03A10LA11LR/WLR/WRA11RA10ROERABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Com’l.–0.5 to +7.0
Mil.–0.5 to +7.0
UnitV
VTERM(2)Terminal Voltage
with Respectto GroundTATBIASTSTGPT(3)IOUT
OperatingTemperatureTemperatureUnder BiasStorage
TemperaturePower DissipationDC Output Current
INDEXA1LA2LA3LA4LA5LA6LA7LA8LA9LI/O0LI/O1LI/O2L6324847444317428419401039IDT71341138L48-1&1237F48-1LCC/Flatpack13361435TOP VIEW (3)1534163317321831192021222324252627282930GNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RI/O3LI/O4LI/O6LI/O7LI/O5LVCCCERA0LOELCELA0RA1RA2RA3RA4RA5RA6RA7RA8RA9RI/O7RI/O6R0 to +70–55 to +125–55 to +125
1.550
–55 to +125–65 to +135–65 to +150
1.550
°C°C°CWmA
2720 tbl 01
2720 drw 04NOTES:
1.All Vcc pins must be connected to the power supply.2.All GND pins must be connected to the ground supply.
3.This text does not indicate orientation of actual part-marking.
NOTES:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGSmay cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability.
2.VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or
10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc+0.5V.
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
SymbolCINCOUT
ParameterInput CapacitanceOutput Capacitance
Conditions(2)VIN = 3dvVOUT = 3dv
Max.1111
UnitpFpF
2720 tbl 02
NOTES:
1.This parameter is determined by device characterization but is notproduction tested.
2.3dv references the interpolated capacitance when the input and outputsignals switch from 0V to 3V and from 3V to 0V.
6.042
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GradeMilitaryCommercial
AmbientTemperature–55°C to +125°C0°C to +70°C
GND0V0V
VCC5.0V ± 10%5.0V ± 10%
2720 tbl 03
RECOMMENDED DC OPERATING CONDITIONS
SymbolVCCGNDVIHVIL
ParameterSupply VoltageGround
Input High VoltageInput Low Voltage
Min.4.502.2–0.5(1)
Typ.5.00——
Max.5.506.0(2)0.8
UnitVVVV
2720 tbl 04
NOTES:
1.VIL (min.) > –1.5V for pulse width less than 10ns.2.VTERM must not exceed Vcc + 0.5V.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (VCC = 5V ± 10%)
IDT7134SA
Symbol|ILI||ILO|VOLVOH
ParameterInput Leakage Current(1)Output Leakage CurrentOutput Low VoltageOutput High Voltage
Test ConditionsVCC = 5.5V, VIN = 0V to VCCCE = VIH, VOUT = 0V to VCCIOL = 6mAIOL = 8mAIOH = –4mA
NOTE:
1.At Vcc ≤ 2.0V input leakages are undefined.
IDT7134LAMin.————2.4
Max.550.40.5—
UnitµAµAVVV
2720 tbl 05
Min.————2.4
Max.10100.40.5—
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
7134X20(4)
SymbolICC
ParameterDynamic OperatingCurrent
(Both Ports Active)
ISB1
Standby Current(Both Ports—TTLLevel Inputs)
ISB2
Standby Current(One Port—TTLLevel Inputs)
ISB3
CE\"A\" = VIL andCE\"B\" = VIH
Test ConditionsCE = VIL
Outputs Openf = fMAX(3)
7134X25
7134X35
7134X45
7134X55
7134X70
VersionTyp.(2)Max.Typ.(2)Max.Typ.(2)Max.Typ.(2)Max.Typ.(2)Max.Typ.(2)Max.UnitMIL.
SL
——170170——2525——105105——1.00.2——105105
——280240——11080——180150——1.5——170130
16016016016025252525959595951.00.21.00.295959595
31015026015028015022015010080805021017018014030101.0210150170120
25252525858585851.00.21.00.285858585
30014025014026014021014075557520016017013030101.0190130160110
25252525757575751.00.21.00.275757575
2802402402007050704019015016013030101.0180120150100
14014014014025252525757575751.00.21.00.275757575
2702202402007050704018015016013030101.0170120150100
14027014022014024014020025252525757575751.00.21.00.275757575
7050704018015016013030101.0170120150100
mAmAmAmAmA
COM’L.S
L
SL
CEL and CER = VIHMIL.f = fMAX(3)
COM’L.S
LMIL.
SL
Active Port OutputsCOM’L.SOpen, f = fMAX(3)L
S
L
Full Standby CurrentBoth Ports CEL andMIL.(Both Ports—AllCER ≥ VCC - 0.2VCMOS Level Inputs)VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V, f = 0(3)
COM’L.S
LMIL.
SL
ISB4
Full Standby CurrentOne Port CE\"A\" or(One Port—AllCE\"B\" ≥ VCC - 0.2V
CMOS Level Inputs)VIN ≥ VCC - 0.2V orCOM’L.S
LVIN ≤ 0.2V
Active Port OutputsOpen, f = fMAX(3)
NOTES:2720 tbl 061.“X” in part number indicates power rating (SA or LA).
2.VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3.fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level
standby ISB3.
4.(Commercial only) 0°C to +70°C temperature range.
6.043
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
SymbolVDRICCDRtCDR(3)tR(3)
Parameter
VCC for Data RetentionData Retention Current
Chip Deselect to Data Retention TimeOperation Recovery Time
Test Condition
VCC = 2VCE ≥ VHC
VIN ≥ VHC or < VLC
MIL.COM’L.
Min.2.0——0tRC(2)
Typ.(1)—100100——
Max.—40001500——
nsns
2720 tbl 07
UnitVµA
NOTES:
1.VCC = 2V, TA = +25°C, and are not production tested.2.tRC = Read Cycle Time.
3.This parameter is guaranteed by device characterization, but not production tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODEVCC4.5VtCDRCEVIHVDRVDR ≥ 2V4.5VtRVIH2720 drw 05
AC TEST CONDITIONS
Input Pulse LevelsInput Rise/Fall Times
Input Timing Reference LevelsOutput Reference LevelsOutput Load
GND to 3.0V
5ns1.5V1.5V
Figures 1 and 2
2720 tbl 08
+5V1250ΩDATAOUT775Ω30pF *2720 drw 06+5V1250ΩDATAOUT775Ω5pF *2720 drw 07Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
6.044
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
7134X20(3)
Symbol READ CYCLEtRCtAAtACEtAOEtOHtLZtHZtPUtPD
Read Cycle TimeAddress Access TimeChip Enable Access TimeOutput Enable Access TimeOutput Hold from Address ChangeOutput Low-Z Time(1, 2)Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)Chip Disable to Power Down Time(2)
20———00—0—
—202015——15—20
25———00—0—
—252515——15—25
35———00—0—
—353520——20—35
nsnsnsnsnsnsnsnsns
Parameter
Min.
Max.
7134X25Min.
Max.
7134X35Min.
Max.
Unit
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4) (CONT'D)
7134X45
Symbol READ CYCLEtRCtAAtACEtAOEtOHtLZtHZtPUtPD
Read Cycle TimeAddress Access TimeChip Enable Access TimeOutput Enable Access TimeOutput Hold from Address ChangeOutput Low-Z Time(1, 2)Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)Chip Disable to Power Down Time(2)
45———05—0—
—4525——20—45
55———05—0—
—555530——25—50
70———05—0—
—707040——30—50
nsnsnsnsnsnsnsnsns
2720 tbl 09
7134X55Min.
Max.
7134X70Min.
Max.
Unit
ParameterMin.Max.
NOTES:
1.Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).2.This parameter is guaranteed by device characterization, but is not production tested.3.(Commercial only) 0°C to +70°C temperature range only.4.“X” in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1, 2, 3)
tRCADDRESStOHDATAOUTPREVIOUS DATA VALIDtAAtOHDATA VALID2720 drw 08NOTES:
1.Timing depends on which signal is asserted last, OE or CE.2.Timing depends on which signal is de-asserted first, OE or CE.3.R/W = VIH.
6.045
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(1, 3)
tACECEtAOE(4)OEtLZ(1)DATAOUTtPU50%tLZ(1)VALID DATA (4)tPD50%2720 drw 09tHZ(2)tHZ(2)ICCCURRENTISBNOTES:
1.Timing depends on which signal is asserted last, OE or CE.2.Timing depends on which signal is de-asserted first, OE or CE.3.R/W = VIH.
4.Start of valid data depends on which timing becomes effective , tAOE, tACE or tAA5.tAA for RAM Address Access and tSAA for Semaphore Address Access.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
Symbol WRITE CYCLEtWCtEWtAWtAStWPtWRtDWtHZtDHtWZtOWtWDDtDDD
NOTES:
ParameterWrite Cycle TimeChip Enable to End-of-WriteAddress Valid to End-of-Write
Address Set-up TimeWrite Pulse WidthWrite RecoveryTimeData Valid to End-of-WriteOutput High-Z Time(1, 2)
Data Hold Time(3)
Write Enabled to Output in High-Z(1, 2)Output Active from End-of-Write(1, 2, 3)
Write Pulse to Data Delay(4)
Write Data Valid to Read Data Delay(4, 7)
7134X20(5)Min.Max.201515015015—0—3——
———————15—15—4030
7134X25
Min.Max.252020020015—0—3——
———————15—15—5030
7134X35
Min.Max.353030025020—3—3——
———————20—20—6035
Unitnsnsnsnsnsnsnsnsnsnsnsnsns
2720 tbl 10
1.Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2.This parameter is guaranteed by device characterization, but is not production tested.
3.The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4.Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.5.(Commercial only), 0°C to +70°C temperature range .6.“X” in part number indicates power rating (SA or LA).7.tDDD = 35ns for military temperature range.
6.046
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6) (CONT'D)
Symbol WRITE CYCLEtWCtEWtAWtAStWPtWRtDWtHZtDHtWZtOWtWDDtDDD
Write Cycle Time
Chip Enable to End-of-WriteAddress Valid to End-of-WriteAddress Set-up TimeWrite Pulse WidthWrite RecoveryTimeData Valid to End-of-WriteOutput High-Z Time(1, 2)Data Hold Time(3)
Write Enabled to Output in High-Z(1, 2)Output Active from End-of-Write(1, 2, 3)Write Pulse to Data Delay(4)
Write Data Valid to Read Data Delay(4)
4040040020—3—3——
———————20—20—7045
555050050025—3—3——
———————25—25—8055
706060060030—3—3——
———————30—30—9070
nsnsnsnsnsnsnsnsnsnsnsnsns
2720 tbl 10
Parameter
7134X45Min.Max.7134X55
Min.Max.7134X70
Min.Max.
Unit
NOTES:
1.Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).2.This parameter is guaranteed by device characterization, but is not production tested.
3.The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4.Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.5.(Commercial only), 0°C to +70°C temperature range .6.“X” in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1)
tWCADDR \"A\"MATCHtWPR/W \"A\"tDWDATAIN \"A\"VALIDtAWADDR \"B\"MATCHtWDDDATAOUT \"B\"tDDDNOTES:
1.Write cycle parameters should be adhered to, in order to ensure proper writing.2.CEL = CER = VIL. OE\"B\" = VIL.
3.Port \"A\" may be either left or right port. Port \"B\" is the opposite from port \"A\".
VALID2720 drw 106.047
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1, 5, 8)
tWCADDRESStAS(6)tAWCEtWP(2)R/WtLZDATAOUT(4)OEtWR(3)tHZ(7)tWZ(7)tOW(4)tHZ(7)tDWDATAINtDH2720 drw 11TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1, 5)
tWCADDRESStAWCEtAS(6)R/WtDWDATAIN2720 drw 12tEW(2) 1.20 in tWR(3)tDHNOTES:
1.R/W or CE must be High during all address transitions.
2.A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3.tWR is measured from the earlier of CE or R/W going High to the end-of-write cycle.
4.During this period, the I/O pins are in the output state, and input signals must not be applied.
5.If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.6.Timing depends on which enable signal ( CE or R/W )is asserted last.
7.This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the OutputTest Load (Figure 2).
8.If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data tobe placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can beas short as the specified tWP.
6.048
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT7134 provides two ports with separate control,address, and I/O pins that permit independent access forreads or writes to any location in memory. These devices havean automatic power down feature controlled by CE. The CEcontrols on-chip power down circuitry that permits therespective port to go into standby mode when not selected(CE high). When a port is enabled, access to the entirememory array is permitted. Each port has its own OutputEnable control (OE). In the read mode, the port’s OE turns onthe output drivers when set LOW. Non-contention READ/WRITE conditions are illustrated in the table below.
TRUTH TABLE I – READ/WRITE CONTROL(2)
Left or Right Port(1)R/WXXLHX
CEHHLLX
OEXXXLH
D0-7ZZDATAINDATAOUT
Z
Function
Port Disabled and in PowerDown Mode, ISB2 or ISB4CER = CEL = H, Power DownMode, ISB1 or ISB3Data on port written intomemory
Data in memory output on portHigh impedance outputs
2720 tbl 11
NOTES:
1.AOL - A11L ≠ AOR - A11R
2.\"H\" = HIGH, \"L\" = LOW, \"X\" = Don’t Care, and \"Z\" = High-impedance
ORDERING INFORMATION
IDTXXXXDevice TypeAPower999SpeedAPackageAProcess/TemperatureRangeBlankBPCJL48F2025355570LASA7134Commercial (0°C to +70°C)Military (–55°C to +125°C)Compliant to MIL-STD-883, Class B48-pin Plastic DIP (P48-1)48-pin Ceramic DIP (C48-2)52-pin PLCC (J52-1)48-pin LCC (L48-1)48-pin Ceramic Flatpack (F48-1)Commercial OnlySpeed in nanosecondsLow PowerStandard Power32K (4K x 8-Bit) Dual-Port RAM2720 drw 136.049
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