Master slice type semiconductor integrated circuit

专利名称：Master slice type semiconductor integrated

circuit and method for designing the same

发明人：Yoshiteru Ono申请号：US10232119申请日：20020830

公开号：US200300035A1公开日：20030109

专利附图：

摘要：A placing and wiring method for a master slice type semiconductor integratedcircuit is provided. The method is conducted by an automatic placing and routingapparatus with respect to a master slice having a plurality of basic cells formed in a

matrix, in which first and second power source wirings and that traverse the plurality ofbasic cells are connected to a plurality of signal wirings that are formed along a verticaldirection to provide connections within each of the plurality of basic cells and/or betweenthe plurality of basic cells The method includes: a first step of registering in the

automatic pacing and routing apparatus definitions of effective pin positions A-A, B-BandC-C; a second step of registering a net list in the automatic placing and routing apparatus;and a third step of determining the placement of pin positions and wiring routes, basedon data for the definitions of the effective pin positions and the net list. The registeredeffective pin positions are provided on lattice grids located inside and outside a regionbetween the first and second power source wirings and In the circuit wired according tothe definitions, contacts with respect to the drains are provided inside and outside theregion between the first and second power source wirings and and the signal wirings donot cross the power source wirings.

申请人：SEIKO EPSON CORPORATION

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