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tps7333

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TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997DAvailable in 3-V, 3.3-V, 4.85-V, and 5-VDDDDDDDD Fixed-Output and Adjustable VersionsIntegrated Precision Supply-VoltageSupervisor Monitoring Regulator OutputVoltageActive-Low Reset Signal with 200-ms PulseWidthVery Low Dropout Voltage...Maximum of35 mV at IO = 100 mA (TPS7350)Low Quiescent Current – Independent ofLoad...340 µA TypExtremely Low Sleep-State Current,0.5 µA Max2% Tolerance Over Full Range of Load,Line, and Temperature for Fixed-OutputVersionsOutput Current Range of 0 mA to 500 mATSSOP Package Option Offers ReducedComponent Height For Critical ApplicationsD OR P PACKAGE(TOP VIEW)GNDENININ12348765RESETSENSE†/FB‡OUTOUTPW PACKAGE(TOP VIEW)GNDGNDGNDNCNCENNCINININ1234 5671020191817161514131211RESETNCNCFB‡NCSENSE†OUTOUTNCNCdescriptionThe TPS73xx devices are members of a family ofmicropower low-dropout (LDO) voltage regulators.They are differentiated from the TPS71xx andTPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is notrequired, the designer should consider the TPS71xx and TPS72xx.§AVAILABLE OPTIONSOUTPUT VOLTAGE(V)TJMIN4.94.75–40°C toC125°C3.232.94TYP.853.33MAX5.14.953.373.06NEGATIVE-GOING RESET THRESHOLD VOLTAGE(V)MIN4.5.52.8682.581.101TYP4.6.62.9342.1.123MAX4.7.732.71.145SMALLOUTLINE(D)TPS7350QDTPS7348QDTPS7333QDTPS7330QDTPS7301QDNC – No internal connection†SENSE – Fixed voltage options only(TPS7330, TPS7333, TPS7348, and TPS7350)‡FB – Adjustable version only (TPS7301)PACKAGED DEVICESCHIP FORM(Y)PLASTIC DIP(P)TPS7350QPTPS7348QPTPS7333QPTPS7330QPTPS7301QPTSSOP(PW)TPS7350QPWLETPS7348QPWLETPS7333QPWLETPS7330QPWLETPS7301QPWLETPS7350YTPS7348YTPS7333YTPS7330YTPS7301YAdjustable1.2 V to 9.75 VThe D package is available taped and reeled. Add R suffix to device type (e.g., TPS7350QDR). The PW package is only available left-end tapedand reeled. The TPS7301Q is programmable using an external resistor divider (see application information). The chip form is tested at 25°C.§The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively, offering performance similar to that of the TPS73xxbut without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin shrink small-outlinepackages (TSSOP) for applications requiring minimum package size.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1997, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONdescription (continued) The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the eventof an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulatorto detect an undervoltage condition on the regulated output voltage.If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low. RESET stays lowfor the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-outbegins. At the completion of the 200-ms delay, RESET goes high.An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performanceis achieved by replacing the typical pnp pass transistor with a PMOS device.Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mVat an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1).Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remainsconstant, independent of output loading (typically 340 µA over the full range of output current, 0 mA to 500mA).These two key specifications yield a significant improvement in operating life for battery-powered systems.The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator,reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.The TPS73xx is offered in 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%over line, load, and temperature ranges (3% for adjustable version). The TPS73xx family is available in PDIP(8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2 mm.0.3TA = 25°C0.25TPS7333Dropout Voltage – V0.20.1 µFTPS7348TPS7330VI106TPS73xxPW†INININENGND0.1TPS73500.05†TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage options)‡Capacitor selection is nontrivial. See application informationsection for details.123RESETSENSEOUTOUT20151413+To SystemReset250 kΩVOCO‡10 µF0.15CSR = 1 Ω0050100150200250300350400450500IO – Output Current – mAFigure 1. Dropout Voltage Versus Output CurrentFigure 2. Typical Application Configuration2POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TPS73xxY chip informationThese chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermalcompression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mountedwith conductive epoxy or a gold-silicon preform.BONDING PAD ASSIGNMENTS(5)(6)(4)INEN(3)(2)TPS73xx(5)(6)(4)(7)(1)(7)GNDCHIP THICKNESS: 15 TYPICAL80BONDING PADS: 4 × 4 MINIMUMTJmax = 150°CTOLERANCES ARE ±10%.ALL DIMENSIONS ARE IN MILS.(1)(2)92(3)†SENSE – Fixed voltage options only (TPS7330, TPS7333,TPS7348, and TPS7350)‡FB – Adjustable version only (TPS7301)NOTE A.For most applications, OUT and SENSE shouldbe tied together as close as possible to the device;for other implementations, refer to SENSE-pinconnection discussion in the applicationsinformation section of this data sheet.SENSE†FB‡OUTRESETfunctional block diagramINEN¶¶¶RESET_+OUT+_DelayedResetRESISTOR DIVIDER OPTIONSDEVICETPS7301TPS7330TPS7333TPS7348TPS7350R10358420726756R2∞233233233233UNITΩkΩkΩkΩkΩNOTE A. Resistors are nominal values only.COMPONENT COUNTMOS transistorsBilpolar transistorsDiodesCapacitorsResistors44141776SENSE§/FBR1VrefR2GND§For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer toSENSE-pin connection discussion in applications information section.¶Switch positions are shown with EN low (active).POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONtiming diagramVI Vres†tVOThresholdVoltageVIT–VIT–tRESETOutput200 msDelay200 msDelayVresVIT+VIT+OutputUndefinedOutputUndefinedt†Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standardsfor semiconductor symbology.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡Input voltage range§, VI, RESET, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 11 VOutput current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 AContinuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2Operating virtual junction temperature range, TJ –55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.§All voltage values are with respect to network terminal ground.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (SEE FIGURE 3)PACKAGEDPPW†TA ≤ 25°CPOWER RATING725 mW1175 mW700 mWDERATING FACTORABOVE TA = 25°C5.8 mW/°C9.4 mW/°C5.6 mW/°C = 70TA 70°CPOWER RATING4 mW752 mW448 mW = 125TA 125°CPOWER RATING145 mW235 mW140 mWDISSIPATION RATING TABLE 2 – CASE TEMPERATURE (SEE FIGURE 4)PACKAGEDPPW†TC ≤ 25°CPOWER RATING2188 mW2738 mW4025 mWDERATING FACTORABOVE TC = 25°C9.4 mW/°C21.9 mW/°C32.2 mW/°C = 70TC 70°CPOWER RATING1765 mW1752 mW2576 mW = 125TC 125°CPOWER RATING1248 mW8 mW805 mW†Refer to Thermal Information section for detailed power dissipation considerations when using theTSSOP package.MAXIMUM CONTINUOUS DISSIPATIONvsFREE-AIR TEMPERATURE1400PD– Maximum Continuous Dissipation – mWPD– Maximum Continuous Dissipation – mW120010008006004002000PW PackageRθJA = 178°C/W48004400400036003200280024002000160012008004000255075100125150TA – Free-Air Temperature – °C25MAXIMUM CONTINUOUS DISSIPATIONvsCASE TEMPERATUREPW PackageRθJC = 37°C/WP PackageRθJA = 106°C/WD PackageRθJA = 172°C/WP PackageRθJC = 46°C/WD PackageRθJC = 57°C/W5075100125150TC – Case Temperature – °CFigure 3Figure 4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONrecommended operating conditionsMINTPS7301QTPS7330QInput voltage, VIplgVI†TPS7333QTPS7348QTPS7350QHigh-level input voltage at EN, VIHLow-level input voltage at EN, VILOutput current range, IO02.53.53.775.25.3320.5500MAX1010101010VVmAVUNIT Operating virtual junction temperature range, TJ–40125°C†Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO,at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads.To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:V+V)VI(min)O(max)DO(maxload)Because the TPS7301 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculatingVDO from rDS(on) is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for therecommended input voltage range for the TPS7301.electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR‡ = 1 Ω), SENSE/FB shorted toOUT (unless otherwise noted)PARAMETERGroundcurrent(activemode)Ground current (active mode)Inputcurrent(standbymode)Input current (standby mode)OutputcurrentlimitOutput current limitPasselement leakage current in standbyPass-element leakage current in standbymodeRESETleakagecurrentRESET leakage currentOutput voltage temperature coefficientThermal shutdown junction temperatureENlogichigh(standbymode)EN logic high (standby mode)ENlogiclow(activemode)EN logic low (active mode)EN hysteresis voltageENinputcurrentEN input currentMinimumVI for active pass elementMinimum VforactivepasselementMinimumVI for valid RESETMinimum VforvalidRESETIO(RESET) = –=–300 300µA0V≤ V0 V VI ≤ 10 V10V2.5 V ≤ VI ≤ 6 V6 V ≤ VI ≤ 10 V27V≤ V2.7 V VI ≤ 10 V10V–40°CC to 125to125°C25°C–40°C to 125°C25°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C1–0.5–0.52.05500.0010.50.52.52.51.51.922.70.50.5TEST CONDITIONS§EN ≤ 0.5 V, 0 mA ≤ IO ≤ 500 mAEN=VI,EN = VVO = 0 V,=0VEN=VI,EN = VVI = VO + 1 V,TJ25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C–40°C to 125°C611650.020.011.20.01MINTYP340MAX4005500.52220.510.50.575UNITµAµAAµAµAppm/°C°CVVmVµAVV27V≤ VVI ≤ 10 V10V2.7 V VI = 10 V=10V27V≤ V2.7 V VI ≤ 10 V10VNormaloperationV at RESET = 10 VNormal operation,VatRESET10V‡CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, anyseries resistance added externally, and PWB trace resistance to Co.§Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.6POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), FBshorted to OUT at device leads (unless otherwise noted)PARAMETERReference voltage (measured at FB)Rfl(dFB)Reference voltage temperaturecoefficientVI = 2.4 V,=24VVI = 2.4 V,=24VVI = 2.9 V,=29VVI = 3.9 V,VI = 5.9 V,InputregulationInput regulationVI = 2.5 V to 10 V, 2.5 V to 10 V,See Note 12.5 V ≤ VI ≤ 10 V,See Note 12.5 V ≤ VI ≤ 10 V,See Note 150µA 50 A≤ IIO ≤ 150 mA150mA150mA≤ I150 mA IO ≤ 500 mA500mA50µA 50 A≤ IIO ≤ 500 mA500mA50 µA ≤ IO ≤ 500 mA50 µA ≤ IO ≤ 500 mA50 µA ≤ IO ≤ 500 mA,IO = 5 mA to 500 mA, 5 mA to 500 mA,IO = 50 50 µA to 500 mA,TEST CONDITIONS‡2.5 V ≤ VI ≤ 10 V,See Note 15 mA ≤ IO ≤ 500 mA,TJ25°C–40°C to 125°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C25°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°CIO = 50 =50µARilrejectionRippleRipple rejectionjif=120Hzf = 120 HzH = 500 mA,IO 500 mA,See Note 1Output noise-spectral densityOutput noise voltageOpilgRESET trip-threshold voltage§RESET hysteresis voltage§RESEToutputlowvoltage§RESET output low voltageFBinputcurrentFB input currentf = 120 HzCo = 4.7 µF10 Hz 10H≤ f f≤ 100 kHz100kHVO(FB) decreasingMeasured at VO(FB)VI = 2.13 V,=213VIO(RESET) = 400 =400µACo = 10 µFCo = 100 µF25°C–40°C to 125°C25°C–40°C to 125°C25°C25°C25°C25°C–40°C to 125°C25°C25°C–40°C to 125°C25°C–40°C to 125°C–10–200.11.101120.10.40.41020484444295741.145VmVVnAµVrmsVµV/√Hz59dB750.320.2331825142522mVmVmV0.520.83MINTYP1.1821.147610.71.21775111.31.30.850.85ΩMAXUNITVVppm/°CPasselement series resistance Pass-element series resistance (See Note 2)OOutputregulationliOutput regulation†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.§Output voltage programmed to 2.5 V with closed-loop configuration (see application information).NOTES:1.When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resultingdropout voltage prevents the regulator from maintaining the specified tolerance range.2.To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on)rDS(on) is a function of both output current and input voltage. This parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For otherprogrammed values, refer to Figure 33.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTION TPS7330Q electrical characteristics at IO = 10 mA, VI = 4 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), SENSEshorted to OUT (unless otherwise noted)PARAMETEROutputvoltageOutput voltageTEST CONDITIONS‡4 V ≤ VI ≤ 10 V,=10mAIO = 10 mA,DropoutvoltageDropout voltageIO = 100 mA,=100mAIO = 500 mA,=500mAPass-elementseriesresistancePass-element series resistanceInputregulationInput regulation(2.94 V VO)/IO,(2.94 V – VIO = 500 mAVI = 4 V to 10 V,=4Vto10V=5mAto500mAIO = 5 mA to 500 mA,OliOutput regulationOutputregulationIO = 50 =50µAA to 500 mA,to500mA4V≤ V4 V VI ≤ 10 V10VIO = 50 =50µARilrejectionRipplejiRipple rejectionf=120HzHf = 120 HzIO = 500 mA=500mAOutput noise-spectral densityf = 120 HzCo = 4.7 µFOpOutput noise voltageilg10H≤ f 10 Hz f≤ 100 kHz100kHVO decreasingVI = 2.6 V,=26VIO(RESET) = –=–0.8 mA08mACo = 10 µFCo = 100 µFRESET trip-threshold voltageRESEToutputlowvoltageRESET output low voltage5 mA ≤ IO ≤ 500 mA=294VVI = 2.94 VVI = 2.94 V=294VVI = 2.94 V=294VVI = 2.94 V, 2.94 V,TJ25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C50µA 50 A≤ IIO ≤ 500 mA500mA4V≤ VVI ≤ 10 V10V4 V 25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C25°C25°C25°C–40°C to 125°C25°C–40°C to 125°C2.584340393622742281592.0.142.70.40.4VVµVrmsVµV/√Hz5353dB282060.526752MIN2.945.2TYP33.06710751004505000.712329326060120ΩmVmVmVmVVMAXUNITV†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.8POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7333Q electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),SENSE shorted to OUT (unless otherwise noted)PARAMETEROutputvoltageOutput voltageTEST CONDITIONS‡4.3 V ≤ VI ≤ 10 V,=10mAIO = 10 mA,DropoutvoltageDropout voltageIO = 100 mA,=100mAIO = 500 mA,=500mAPass-elementseriesresistancePass-element series resistanceInputregulationInput regulation(3.23 V VO)/IO,(3.23 V – VIO = 500 mAVI = 4.3 V to 10 V,=43Vto10V5 mA ≤ IO ≤ 500 mA=323VVI = 3.23 VVI = 3.23 V=323VVI = 3.23 V=323VVI = 3.23 V, 3.23 V,TJ25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C50µA 50 A≤ IIO ≤ 500 mA500mA25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°CCo = 4.7 µFOpOutput noise voltageilg10H≤ f 10 Hz f≤ 100 kHz100kHVO decreasingCo = 10 µFCo = 100 µFRESET trip-threshold voltageRESET hysteresis voltageRESEToutputlowvoltageRESET output low voltageVI = 2.8 V,=28VIO(RESET) = –=–11 mAmA25°C25°C25°C–40°C to 125°C25°C25°C–40°C to 125°C2.868180.170.40.4434039362274228159VmVVµVrmsVµV/√Hz4951dB312160.44234MIN3.234.5TYP3.33.377860803004000.60.82329387560120ΩmVmVmVmVVMAXUNITV=5mAto500mA43V≤ VVI ≤ 10 V10VIO = 5 mA to 500 mA, 4.3 V OliOutput regulationOutputregulationIO = 50 =50µAA to 500 mA, to500mA44.3 V 3V≤ VVI ≤ 10 V10VIO = 50 =50µARilrejectionRipplejiRipple rejectionf=120HzHf = 120 HzIO = 500 mA=500mAOutput noise-spectral densityf = 120 Hz†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTION TPS7348Q electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),SENSE shorted to OUT (unless otherwise noted)PARAMETEROutputvoltageOutput voltageTEST CONDITIONS‡5.85 V≤VI ≤ 10 V,=10mAIO = 10 mA,DropoutvoltageDropout voltageIO = 100 mA,=100mAIO = 500 mA,=500mAPass-elementseriesresistancePass-element series resistanceInputregulationInput regulation(4.75 V VO)/IO,(4.75 V – VIO = 500 mAVI = 5.85 V to 10 V,=585Vto10V5 mA ≤ IO ≤ 500 mA=475VVI = 4.75 VVI = 4.75 V=475VVI = 4.75 V=475VVI = 4.75 V, 4.75 V,TJ25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C50µA 50 A≤ IIO ≤ 500 mA500mA25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°CCo = 4.7 µFOpOutput noise voltageilg10H≤ f 10 Hz f≤ 100 kHz100kHVO decreasingCo = 10 µFCo = 100 µFRESET trip-threshold voltageRESET hysteresis voltageRESEToutputlowvoltageRESET output low voltageIO(RESET) = –=–1.2 mA,V12mAVI = 4.12 V=412V25°C25°C25°C–40°C to 125°C25°C25°C–40°C to 125°C4.5260.20.40.44239393524103282124.7VmVVµVrmsVµV/√Hz5053dB4220.2815028MIN4.752.9TYP4.8.9568371802500.370.523537428065130ΩmVmVmVmVVMAXUNITV=5mAto500mA585V≤ VVI ≤ 10 V10VIO = 5 mA to 500 mA, 5.85 V OliOutput regulationOutputregulationIO = 50 =50µAA to 500 mA, to500mA55.85 V 85V≤ VVI ≤ 10 V10VIO = 50 =50µARilrejectionRipplejiRipple rejectionf=120HzHf = 120 HzIO = 500 mA=500mAOutput noise-spectral densityf = 120 Hz†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.10POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7350Q electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), SENSEshorted to OUT (unless otherwise noted)PARAMETEROutputvoltageOutput voltageTEST CONDITIONS‡6 V≤VI ≤ 10 V,=10mAIO = 10 mA,DropoutvoltageDropout voltageIO = 100 mA,=100mAIO = 500 mA,=500mAPass-elementseriesresistancePass-element series resistanceInputregulationInput regulation(4.88 V VO)/IO,(4.88 V – VIO = 500 mAVI = 6 V to 10 V,=6Vto10V=5mAto500mAIO = 5 mA to 500 mA,OliOutput regulationOutputregulationIO = 50 =50µAA to 500 mA,to500mA6V≤ V6 V VI ≤ 10 V10VIO = 50 =50µARilrejectionRipplejiRipple rejectionf=120HzHf = 120 HzIO = 500 mA=500mAOutput noise-spectral densityf = 120 HzCo = 4.7 µFOpOutput noise voltageilg10H≤ f 10 Hz f≤ 100 kHz100kHVO decreasingCo = 10 µFCo = 100 µFRESET trip-threshold voltageRESET hysteresis voltageRESEToutputlowvoltageRESET output low voltageIO(RESET) = –=–1.2 mA, 12mAVI = 4.25 V=425V5 mA ≤ IO ≤ 500 mA=488VVI = 4.88 VVI = 4.88 V=488VVI = 4.88 V=488VVI = 4.88 V, 4.88 V,TJ25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C50µA 50 A≤ IIO ≤ 500 mA500mA6V≤ VVI ≤ 10 V10V6 V 25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C–40°C to 125°C25°C25°C25°C25°C–40°C to 125°C25°C25°C–40°C to 125°C4.55280.150.40.44338413624303452204.75VmVVµVrmsVµV/√Hz5153dB453040.2714627MIN4.92.9TYP55.16835501702300.350.5258665140ΩmVmVmVmVVMAXUNITV†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•11SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONswitching characteristicsPARAMETERTEST CONDITIONSTJ25°C–40°C to 125°CTPS7301Q, TPS7333QTPS7348Q, TPS7350QMINRESETtime-outdelayRESET time-out delaySeeFigure5See Figure 5140100TYP200MAX260300msUNIT electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE/FBshorted to OUT (unless otherwise noted)PARAMETERTEST CONDITIONS‡EN ≤ 0.5 V,0 mA ≤ IO ≤ 500 mAEN = VI,VO = 0 V,EN = VI,Normal operation,2.7 V ≤ VI ≤ 10 V500 V ≤ VI ≤ 10 V0.0012.05VI = VO + 1 V,2.7 V ≤ VI ≤ 10 VVI = 10 V2.7 V ≤ VI ≤ 10 VV at RESET = 10 VTPS7301Y, TPS7333YTPS7348Y, TPS7350YMINGround current (active mode)Input current (standby mode)Output current limitPass-element leakage current in standby modeRESET leakage currentThermal shutdown junction temperatureEN logic low (active mode)EN hysteresis voltageEN input currentMinimum VI for active pass elementTYP3400.011.20.010.021650.5MAXµAµAAµAµA°CVmVµAVUNITIO(RESET) = –300 µA1VMinimum VI for valid RESET†CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, anyseries resistance added externally, and PWB trace resistance to Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.12POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Y electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, FB shorted to OUT at device leads (unless otherwise noted)PARAMETERReference voltage (measured at FB)VI = 2.4 V,VI = 2.4 V,Pass-element series resistance (See Note 2)()VI = 2.9 V,VI = 3.9 V,VI = 5.9 V,VI = 2.5 V to 10 V,See Note 12.5 V ≤ VI ≤ 10 V,See Note 12.5 V ≤ VI ≤ 10 V,See Note 1f = 120 Hzf120Hf = 120 HzCo = 4.7 µFOutput noise voltageOpilgRESET hysteresis voltage§RESET output low voltage§FB input current10 Hz 10H≤ f f≤ 100 kHz100kHMeasured at VO(FB)VI = 2.13 V,IO(RESET) = 400 µACo = 10 µFCo = 100 µF50 µA ≤ IO ≤ 150 mA150 mA ≤ IO ≤ 500 mA50 µA ≤ IO ≤ 500 mA50 µA ≤ IO ≤ 500 mA50 µA ≤ IO ≤ 500 mA50 µA ≤ IO ≤ 500 mA,IO = 5 mA to 500 mA,IO = 50 µA to 500 mA,IO = 50 µAIO = 500 mA,See Note 1TEST CONDITIONS‡MINTYP1.1820.70.830.520.320.233575929574120.10.1mVVnAµVrmsVdBµV/√HzmVmVmVΩMAXUNITVInput regulationOutputregulationOutput regulationRipple rejectionRiljiOutput noise-spectral density†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.§Output voltage programmed to 2.5 V with closed-loop configuration (see application information).NOTES:1.When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resultingdropout voltage prevents the regulator from maintaining the specified tolerance range.2.To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on)rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For otherprogrammed values, refer to Figure 33.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•13SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTPS7330Y electrical characteristics at IO = 10 mA, VI = 4 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)PARAMETEROutput voltageDropout voltagepgIO = 10 mA,IO = 100 mA,IO = 500 mA,(2.94 V – VO)/IO,IO = 500 mAVI = 4 V to 10 V,IO = 5 mA to 500 mA,IO = 50 µA to 500 mA,f=120Hzf = 120 Hzf = 120 HzCo = 4.7 µFOpOutput noise voltageilg10H≤ f 10 Hz f≤ 100 kHz100kHVI = 2.6 V,Co = 10 µFCo = 100 µFRESET output low voltageIO(RESET) = –0.8 mAVI = 2.94 VVI = 2.94 VVI = 2.94 VVI = 2.94 V,50 µA ≤ IO ≤ 500 mA4 V ≤ VI ≤ 10 V4 V ≤ VI ≤ 10 VIO = 50 µAIO = 500 mATEST CONDITIONS‡MINTYP35.2522670.562028535322742281590.14VµVrmsVΩmVmVmVdBµV/√HzmVVMAXUNITV Pass-element series resistanceInput regulationOutputregulationOutput regulationRipplerejectionRipple rejectionOutput noise-spectral density†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.TPS7333Y electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)PARAMETEROutput voltageDropout voltagepgIO = 10 mA,IO = 100 mA,IO = 500 mA,(3.23 V – VO)/IO,IO = 500 mAVI = 4.3 V to 10 V,IO = 5 mA to 500 mA,IO = 50 µA to 500 mA,f=120Hzf = 120 Hzf = 120 HzCo = 4.7 µFOpOutput noise voltageilg10H≤ f 10 Hz f≤ 100 kHz100kHCo = 10 µFCo = 100 µFRESET hysteresis voltageRESET output low voltageVI = 2.8 V,IO(RESET) = –1 mAVI = 3.23 VVI = 3.23 VVI = 3.23 VVI = 3.23 V,50 µA ≤ IO ≤ 500 mA4.3 V ≤ VI ≤ 10 V4.3 V ≤ VI ≤ 10 VIO = 50 µAIO = 500 mATEST CONDITIONS‡MINTYP3.34.42350.446213151492274228159180.17mVVµVrmsVΩmVmVmVdBµV/√HzmVVMAXUNITVPass-element series resistanceInput regulationOutputregulationOutput regulationRipplerejectionRipple rejectionOutput noise-spectral density†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.14POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7348Y electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)PARAMETEROutput voltageDropout voltagepgIO = 10 mA,IO = 100 mA,IO = 500 mA,(4.75 V – VO)/IO,IO = 500 mAVI = 5.85 V to 10 V,IO = 5 mA to 500 mA,IO = 50 µA to 500 mA,f=120Hzf = 120 Hzf = 120 HzCo = 4.7 µFOutput noise voltageOilgp10H≤ f 10 Hz f≤ 100 kHz100kHCo = 10 µFCo = 100 µFRESET hysteresis voltageVI = 4.75 VVI = 4.75 VVI = 4.75 VVI = 4.75 V,50 µA ≤ IO ≤ 500 mA5.85 V ≤ VI ≤ 10 V5.85 V ≤ VI ≤ 10 VIO = 50 µAIO = 500 mATEST CONDITIONS‡MINTYP4.852.9281500.228425350241032821226mVVµVrmsΩmVmVmVdBµV/√HzmVVMAXUNITVPass-element series resistanceInput regulationOutputregulationOutput regulationRipplerejectionRipple rejectionOutput noise-spectral densityIO(RESET) = –1.2 mA,VI = 4.12 V0.2VRESET output low voltage†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•15SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTPS7350Y electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted)PARAMETEROutput voltageDropout voltagepgIO = 10 mA,IO = 100 mA,IO = 500 mA,(4.88 V – VO)/IO,IO = 500 mAVI = 6 V to 10 V,IO = 5 mA to 500 mA,IO = 50 µA to 500 mA,f=120Hzf = 120 Hzf = 120 HzCo = 4.7 µFOpOutput noise voltageilg10H≤ f 10 Hz f≤ 100 kHz100kHCo = 10 µFCo = 100 µFRESET hysteresis voltageRESET output low voltageIO(RESET) = –1.2 mA,VI = 4.25 VVI = 4.88 VVI = 4.88 VVI = 4.88 VVI = 4.88 V,50 µA ≤ IO ≤ 500 mA6 V ≤ VI ≤ 10 V6 V ≤ VI ≤ 10 VIO = 50 µAIO = 500 mATEST CONDITIONS‡MINTYP52.9271460.274284153512430345220280.150.4mVVµVrmsV6351700.352575ΩmVmVmVdBµV/√HzmVVMAXUNITV Pass-element series resistanceInput regulationOutputregulationOutput regulationRipplerejectionRipple rejectionOutput noise-spectral density†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistanceto Co.‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects mustbe taken into account separately.16POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997PARAMETER MEASUREMENT INFORMATIONVOVIT+tVIINENRESETSENSEOUT0.1 µFGND+VO10 µFCSRtTEST CIRCUITVOLTAGE WAVEFORMSRESETRESETTimeout DelayResetFigure 5. Test Circuit and Voltage WaveformsTo LoadOUTSENSEENGNDCSR+COCcer†RLVIIN†Ceramic capacitorFigure 6. Test Circuit for Typical Regions of Stability (Refer to Figures 29 through 32)POST OFFICE BOX 655303 DALLAS, TEXAS 75265•17SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTYPICAL CHARACTERISTICSTable of GraphsFIGUREIQIQVDO∆VDOVDO∆VOVOVOVOVOVOVOQuiescentcurrentQuiescent currentQuiescent current (TPS7348)Dropout voltageChange in dropout voltageDropout voltage (TPS7301 only)Change in output voltageOutput voltageLine regulationOutput voltage (TPS7301)Output voltage (TPS7330)Output voltage (TPS7333)Output voltage (TPS7348)Output voltage (TPS7350)Output voltage response from enable (EN)Load transient response (TPS7301 or TPS7333)Load transient response (TPS7348 or TPS7350)Line transient response (TPS7301)Line transient response (TPS7333)Line transient response (TPS7348 or TPS7350)Ripple rejectionOutput spectral noise densityvs Frequencyvs Frequencyvs Output current (Co = 4.7 µF)CCompensationCompensation series resistance (CSR)iseriesiresistancei(CSR)vs Added ceramic capacitance (Co = 4.7 µF)vs Output current (Co = 10 µF)vs Added ceramic capacitance (Co = 10 µF)rDS(on)VIVIT–IOL(RESET)tdtdPass-element resistanceMinimum input voltage for valid RESETNegative-going reset thresholdRESET output currentReset time delayDistribution for reset delayvs Input voltagevs Free-air temperaturevs Free-air temperaturevs Input voltagevs Free-air temperaturevs Output currentvs Output currentvs Output currentvs Output currentvs Output currentvs Output currentvs Input voltagevs Free-air temperaturevs Output currentvs Free-air temperaturevs Output currentvs Free-air temperaturevs Input voltage71011121314151617181920212223242526272829303132333435363738 18POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TYPICAL CHARACTERISTICSQUIESCENT CURRENTvsOUTPUT CURRENT450425IQ– Quiescent Current –µA400375350325300TPS7330, VI = 4 V275050100150200250TPS7350, VI = 6 VTPS7348, VI = 5.85 VTPS7333, VI = 4.3 V500TA = 25°CTPS73xx, VI = 10 VIQ– Quiescent Current –µA450400TPS73333503002502001501005000123456710TPS7301 With VOProgrammed to 2.5 VTPS7348TPS7350TA = 25°CIO = 500 mAQUIESCENT CURRENTvsINPUT VOLTAGEIO – Output Current – mAVI – Input Voltage – VFigure 7TPS7348QUIESCENT CURRENTvsFREE-AIR TEMPERATURE500VI = 5.85 VIO = 500 mA0.250.3TA = 25°CFigure 8DROPOUT VOLTAGEvsOUTPUT CURRENTTPS7330TPS7333450IQ– Quiescent Current –µA400Dropout Voltage – V0.23500.15TPS73483000.1TPS73502500.05200–50–2502550751001250050100150200250300350400450500IO – Output Current – mATA – Free-Air Temperature – °CFigure 9Figure 10POST OFFICE BOX 655303 DALLAS, TEXAS 75265•19SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTYPICAL CHARACTERISTICSCHANGE IN DROPOUT VOLTAGEvsFREE-AIR TEMPERATURE10∆VDO– Change In Dropout Voltage – mV820–2–4–6–8–10–50–250255075100125VDO– Dropout Voltage – V1.2VI = 2.9 V10.80.60.40.20VI = 3.2 VVI = 3.9 VVI = 5.9 VVI = 9.65 VVI = 2.6 VIO = 100 mA1.6TA = 25°C1.4VI = 2.4 VTPS7301 DROPOUT VOLTAGEvsOUTPUT CURRENT050TA – Free-Air Temperature – °C100150200IO – Output Current – mA250Figure 11CHANGE IN OUTPUT VOLTAGEvsFREE-AIR TEMPERATURE20151050–5–10–15–20–500–250255075100125TA – Free-Air Temperature – °C0126VI = VO(nom) + 1 VIO = 100 mA5VO– Output Voltage – VTA = 25°CIO = 500 mAFigure 12OUTPUT VOLTAGEvsINPUT VOLTAGETPS7350∆VO– Change in Output Voltage – mVTPS734843TPS7333TPS7301 With VOProgrammed to 2.5 V213456710VI – Input Voltage – VFigure 13Figure 1420POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TYPICAL CHARACTERISTICSTPS7301LINE REGULATION20∆VO– Change In Output Voltage – mV151050–5–10–15–2045867VI – Input Voltage – V910TPS7333TPS7350TPS7348TA = 25°CIO = 250 mA2.522.5152.512.5052.52.4952.492.4852.48OUTPUT VOLTAGEvsOUTPUT CURRENTTA = 25°CVO Programmed to 2.5 VVO– Output Voltage – VVI = 3.5 VVI = 10 V0100200300400500IO – Output Current – mAFigure 15TPS7330Figure 16TPS7333OUTPUT VOLTAGEvsOUTPUT CURRENT3.153.123.09VO– Output Voltage – V3.063.0332.972.942.912.882.850100200300400500VO– Output Voltage – VTA = 25°COUTPUT VOLTAGEvsOUTPUT CURRENT3.34TA = 25°C3.333.323.313.33.293.283.273.26VI = 10 VVI = 4.3 V0100200300400500IO – Output Current – mAIO – Output Current – mAFigure 17Figure 18POST OFFICE BOX 655303 DALLAS, TEXAS 75265•21SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTYPICAL CHARACTERISTICSTPS7348TPS7350 OUTPUT VOLTAGEvsOUTPUT CURRENT4.924.914.9VO– Output Voltage – VVO– Output Voltage – V4.4.884.874.8.8.844.834.824.814.80100200300400500VI = 10 VVI = 5.85 VTA = 25°C5.065.055.045.035.025.01.994.984.974.9.9.94IO – Output Current – mA0100TA = 25°COUTPUT VOLTAGEvsOUTPUT CURRENTVI = 6 VVI = 10 V400300200IO – Output Current – mA500Figure 19OUTPUT VOLTAGE RESPONSE FROMENABLE (EN)VO– Output Voltage – V20TA = 25°CRL = 500 ΩCo = 4.7 µF (CSR = 1Ω)No Input CapacitanceVO(nom)Figure 2020–2EN Voltage – V020406080100120140Time – µsFigure 2122POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TYPICAL CHARACTERISTICSTPS7301 (WITH VO PROGRAMMED TO 2.5 V) OR TPS7333∆VO– Change in Output Voltage – mVLOAD TRANSIENT RESPONSE2001000–100–200TA = 25°CVI = 6 VCI = 0Co = 4.7 µF (CSR = 1 Ω)105555–455000100200300400t – Time – µsFigure 22TPS7348 OR TPS7350∆VO– Change in Output Voltage – mVLOAD TRANSIENT RESPONSE2001000–100–200TA = 25°CVI = 6 VCI = 0Co = 4.7 µF (CSR = 1 Ω)105555–455000100200300400t – Time – µsFigure 23POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IO– Output Current – mAIO– Output Current – mA23SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTYPICAL CHARACTERISTICS∆VO– Change in Output Voltage – mVTPS7301 WITH VO PROGRAMMED TO 2.5 V LINE TRANSIENT RESPONSE100500–50–100TA = 25°CCI = 0Co = 4.7 µF (CSR = 1 Ω)6.56.2565.700VI– Input Voltage – VVI– Input Voltage – V0100200300t – Time – µsFigure 24TPS7333∆VO– Change in Output Voltage – mVLINE TRANSIENT RESPONSE2001000–50–100TA = 25°CCI = 0Co = 4.7 µF (CSR = 1 Ω)6.56.2565.755000100200300400t – Time – µsFigure 2524POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TYPICAL CHARACTERISTICSTPS7348 OR TPS7350∆VO– Change in Output Voltage – mVLINE TRANSIENT RESPONSE100500–50–100TA = 25°CCI = 0Co = 4.7 µF (CSR = 1 Ω)6.56.2565.755000100200300400t – Time – µsFigure 26RIPPLE REJECTIONvsFREQUENCY60TPS7333TA = 25°CNo InputCapacitance AddedVI = VO + 1 VIO = 100 mACo = 4.7 µF (CSR = 1)TPS7301 WithVO Programmedto 2.5 V50Ripple Rejection – dB40TPS7348/TPS73503020100101001 K10 K100 K1 M10 Mf – Frequency – HzFigure 27POST OFFICE BOX 655303 DALLAS, TEXAS 75265•VI– Input Voltage – V25SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTYPICAL CHARACTERISTICSOUTPUT SPECTRAL-NOISE DENSITYvsFREQUENCY10Output Spectral-Noise Density – µV/HzTA = 25°CNo Input Capacitance AddedVI = VO + 1 VCo = 4.7 µF (CSR = 1 Ω)Co = 10 µF (CSR = 1 Ω) 10.1Co = 100 µF (CSR = 1 Ω)0.01101001 k10 kf – Frequency – Hz100 kFigure 28TYPICAL REGIONS OF STABILITYTYPICAL REGIONS OF STABILITYCOMPENSATION SERIES RESISTANCE (CSR)†vsOUTPUT CURRENT100CSR – Compensation Series Resistance – ΩRegion of InstabilityCSR – Compensation Series Resistance – ΩCOMPENSATION SERIES RESISTANCE (CSR)†vsADDED CERAMIC CAPACITANCE100Region ofInstabilityTA = 25°CVI = VO + 1 VIO = 500 mACo = 4.7 µFNo Input Capacitor Added1010110.1TA = 25°CVI = VO + 1 VCo = 4.7 µFNo Added Ceramic CapacitanceNo Input Capacitance AddedRegion of Instability050100150200250IO – Output Current – mA0.1Region of Instability0.010.0100.10.20.30.40.50.60.70.80.91Added Ceramic Capacitance – µFFigure 29Figure 3026POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997TYPICAL CHARACTERISTICSTYPICAL REGIONS OF STABILITYTYPICAL REGIONS OF STABILITYCOMPENSATION SERIES RESISTANCE (CSR)†vsOUTPUT CURRENT100CSR – Compensation Series Resistance – ΩCSR – Compensation Series Resistance – ΩRegion of InstabilityCOMPENSATION SERIES RESISTANCE (CSR)†vsADDED CERAMIC CAPACITANCE100Region ofInstabilityTA = 25°CVI = VO + 1 VIO = 500 mACo = 10 µFNo Input Capacitor Added10101TA = 25°CVI = VO + 1 VCo = 10 µFNo Added Ceramic CapacitanceNo Input Capacitor Added10.1Region of Instability0.010.1Region of Instability0.0105010015020025000.10.20.30.40.50.60.70.80.91IO – Output Current – mAAdded Ceramic Capacitance – µFFigure 31PASS-ELEMENT RESISTANCEvsINPUT VOLTAGE10.90.80.70.60.50.40.30.20.12345768VI – Input Voltage – V910IO = 100 mAIO = 500 mATA = 25°CVI(FB) = 1.12 VVI– Minimum Input Voltage For Valid RESET – V1.1rDS(on)– Pass-Element Resistance –ΩFigure 32MINIMUM INPUT VOLTAGE FOR VALID RESETvsFREE-AIR TEMPERATURE1.11.091.081.071.061.05–50–250255075100TA – Free-Air Temperature – °C125Figure 33Figure 34POST OFFICE BOX 655303 DALLAS, TEXAS 75265•27SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTYPICAL CHARACTERISTICSNEGATIVE-GOING RESET THRESHOLDvsFREE-AIR TEMPERATURE15VIT–– Negative-Going Reset Threshold – mV43.5IOL – RESET Output Current – mA1032.52TPS73501.510.5–15–500TPS7348TPS7333IL = 10 mAVOL ≤ 0.4 VTA = 25°C RESET OUTPUT CURRENTvsINPUT VOLTAGE50–5–10–2502550751001250123456710TA – Free-Air Temperatu°Cre – VI – Input Voltage – VFigure 35RESET DELAY TIMEvsFREE-AIR TEMPERATURE197196td– Reset Delay Time – msPercentage of Units – %195194193192191190–50504035302520151050180Figure 36DISTRIBUTION FOR RESET DELAYTA = 25°C197 Devices–250255075100TA – Free-Air Temperature –°C125185200205190195td – Reset Delay Time – ms210Figure 37Figure 3828POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997THERMAL INFORMATIONIn response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitchsurface-mount packages. Implementation of many of today’s high-performance devices in these packages requiresspecial attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heatsinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipationlimits of a given component.Three basic approaches for enhancing thermal performance are illustrated in this discussion:DImproving the power-dissipation capability of the PWB designDImproving the thermal coupling of the component to the PWBDIntroducing airflow in the systemFigure 39 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involvesadding copper on the PWB to conduct heat away from the device. The RθJA (thermal resistance, junction-to-ambient)for this component/board system is illustrated in Figure 40. The family of curves illustrates the effect of increasingthe size of the copper-heat-sink surface area. The PWB is a standard FR4 board (L × W × H = 3.2 inch × 3.2 inch× 0.062 inch); the board traces and heat sink area are 1-oz (per square foot) copper.Figure 41 shows the thermal resistance for the same system with the addition of a thermally conductive compoundbetween the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermalconductivity for the compound used in this analysis is 0.815 W/m × °C.Using these figures to determine the system RθJA allows the maximum power-dissipation limit to be calculated withthe equation:*TJ(max)AP+D(max)RqJA(system)WhereTTJ(max) is the maximum allowable junction temperature; 150°C absolute maximum and 125°Cmaximum recommended operating temperature for specified operation.This limit should then be applied to the internal power dissipated by the TPS73xx regulator. The equation forcalculating total internal power dissipation of the TPS73xx is:PD(total)+V*V I)V IIIOOQǒǓBecause the quiescent current of the TPS73xx family is very low, the second term is negligible, further simplifyingthe equation to:PD(total) I+V*VIOOǒǓFor a 20-lead TSSOP/FR4 board system with thermally conductive compound between the board and the devicebody, where TA = 55°C, airflow = 100 ft/min, and copper heat sink area = 1 cm2, the maximum power-dissipation limitcan be calculated. As indicated in Figure 41, the system RθJA is 94°C/W; therefore, the maximum power-dissipationlimit is:*TJ(max)A°°P++125C*55C+745mWD(max)R94°CńWqJA(system)TIf the system implements a TPS7348 regulator where VI = 6 V and IO = 150 mA, the internal power dissipation is:PD(total)+V*V I+(6*4.85) 0.150+173mWIOOǒǓPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•29SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONTHERMAL INFORMATION Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the maximumlimit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be raised by increasingeither the airflow or the heat-sink area. Alternatively, the internal power dissipation of the regulator can be loweredby reducing either the input voltage or the load current. In either case, the above calculations should be repeated withthe new system parameters.Copper Heat Sink1 oz CuFigure 39. Thermally Enhanced PWB Layout (not to scale) for the 20-Pin TSSOPTHERMAL RESISTANCE, JUNCTION-TO-AMBIENTvsAIR FLOW1901701 cm21502 cm2130110907050050100150200250300Air Flow – ft/minComponent/Board System20-Lead TSSOP0 cm2RθJA– Thermal Resistance, Junction-to-Ambient –°C/WTHERMAL RESISTANCE, JUNCTION-TO-AMBIENTvsAIR FLOWRθJA– Thermal Resistance, Junction-to-Ambient –°C/W190170150130110907050050100150200250300Air Flow – ft/min8 cm20 cm2Component/Board System20-Lead TSSOPIncludes Thermally ConductiveCompound Between Body and Board4 cm22 cm21 cm24 cm28 cm2Figure 40Figure 4130POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997APPLICATION INFORMATIONThe TPS73xx series of low-dropout (LDO) regulators overcome many of the shortcomings of earlier generationLDOs, while adding features such as a power-saving shutdown mode and a supply-voltage supervisor. TheTPS73xx family includes three fixed-output voltage regulators: the TPS7333 (3.3 V), the TPS7348 (4.85 V), andthe TPS7350 (5 V). The family also offers an adjustable device, the TPS7301 (adjustable from 1.2 V to9.75 V).device operationThe TPS73xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant evenwith varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directlyproportional to the load current through the regulator (IB = IC/β). Close examination of the data sheets revealsthat such devices are typically specified under near no-load conditions; actual operating currents are muchhigher as evidenced by typical quiescent current versus load current curves (see Figure 7). The TPS73xx usesa PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currentsare low and invariable over the full load range. The TPS73xx specifications reflect actual performance underload.Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes intodropout. The resulting drop in β forces an increase in IB to maintain the load. During power-up, this translatesto large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,it means rapid battery discharge when the voltage decays below the minimum required for regulation. TheTPS73xx quiescent current remains low even when the regulator drops out, thus eliminating both problems.Included in the TPS73xx family is a 4.85-V regulator, the TPS7348. Designed specifically for 5-V cellularsystems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systemsspecified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery packbefore the device drops out, adding crucial talk minutes between charges.The TPS73xx family also features a shutdown mode that places the output in the high-impedance state(essentially equal to the feedback-divider resistance) and reduces quiescent current to under 0.5 µA. When theshutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulatedoutput voltage is reestablished in typically 120 µs.minimum load requirementsThe TPS73xx family is stable even at zero load; no minimum load is required for operation.SENSE connectionThe SENSE terminal of fixed-output devices must be connected to the regulator output for proper functioningof the regulator. Normally, this connection should be as short as possible; however, the connection can be madenear a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to ahigh-impedance wide-bandwidth amplifier through a resistor-divider network, and noise pickup feeds throughto the regulator output. It is essential to route the SENSE connection in such a way as to minimize/avoid noisepickup. Adding an RC network between SENSE and OUT to filter noise is not recommended because it cancause the regulator to oscillate.external capacitor requirementsAn input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves loadtransient response and noise rejection when the TPS73xx is located more than a few inches from the powersupply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) loadtransients with fast rise times are anticipated.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•31SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONAPPLICATION INFORMATIONexternal capacitor requirements (continued) As with most LDO regulators, the TPS73xx family requires an output capacitor for stability. A low-ESR 10-µFsolid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over thefull load range (see Figure 42). Adding high-frequency ceramic or film capacitors (such as power-supply bypasscapacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalumcapacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as theAVX TPSD106M035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when thetemperature drops from 25°C to –40°C). Where component height and/or mounting area is a problem,physically smaller, 10-µF devices can be screened for ESR. Figures 29 through 32 show the stable regions ofoperation using different values of output capacitance with various values of ceramic load capacitance.In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can bereduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because capacitor minimum ESR isseldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limitESR to 1.5 Ω maximum. As shown in the CSR graphs (Figures 29 through 32), minimum ESR is not a problemwhen using 10-µF or larger output capacitors.Below is a partial listing of surface-mount capacitors usable with the TPS73xx family. This information, alongwith the CSR graphs, is included to assist in selection of suitable capacitance for the user’s application. Whennecessary to achieve low height requirements along with high output current and/or high ceramic loadcapacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.All load and temperature conditions with up to 1 µF of added ceramic load capacitance:PART NO.T421C226M010AS593D156X0025D2W593D106X0035D2WMFR.KemetSpragueSpragueVALUE22 µF, 10 V15 µF, 25 V10 µF, 35 V10 µF, 35 VVALUE15 µF, 20 V15 µF, 25 V10 µF, 25 V22 µF, 16 VVALUE10 µF, 6.3 V10 µF, 16 V15 µF, 16 V22 µF, 15 V15 µF, 20 V10 µF, 35 VMAX ESR†0.50.30.30.3MAX ESR†1.111.21.1MAX ESR†1.51.51.81.41.51.3SIZE (H × L × W)†2.8 × 6 × 3.22.8 × 7.3 × 4.32.8 × 7.3 × 4.32.8 × 7.3 × 4.3SIZE (H × L × W)†1.2 × 7.2 × 62.5 × 7.1 × 3.22.5 × 7.1 × 3.22.8 × 7.3 × 4.3SIZE (H × L × W)†1.3 × 3.5 × 2.71.3 × 7 × 2.71.6 × 3.8 × 2.61.8 × 6.5 × 3.41.8 × 6.5 × 3.42.5 × 7.6 × 2.5TPSD106M035R0300AVXPART NO.592D156X0020R2T595D156X0025C2T595D106X0025C2T293D226X0016D2WPART NO.195D106X06R3V2T195D106X0016X2T595D156X0016B2T695D226X0015F2T695D156X0020F2T695D106X0035G2TMFR.SpragueSpragueSpragueSpragueMFR.SpragueSpragueSpragueSpragueSpragueSpragueLoad < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range:Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range:†Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25°C. Listings are sorted by height.32POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997APPLICATION INFORMATIONexternal capacitor requirements (continued)TPS73xxPW†VI100.1 µF6INININENGND123RESETSENSEOUTOUT20151413+10 µFTo SystemReset250 kΩVOCSR = 1 Ω†TPS7333, TPS7348, TPS7350 (fixed-voltage options)Figure 42. Typical Application Circuitprogramming the TPS7301 adjustable LDO regulatorProgramming the adjustable regulators is accomplished using an external resistor divider as shown inFigure 43. The equation governing the output voltage is:VO+Vref 1)R1R2ǒǓwhereVref = reference voltage, 1.182 V typPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•33SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONAPPLICATION INFORMATION Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherentadvantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents atFB will introduce an error. Solving for R1 yields a more useful equation for choosing the appropriate resistance:R1+ǒO*1VrefVǓ R2OUTPUT VOLTAGEPROGRAMMING GUIDETo SystemReset250 kΩVOR1FBGNDR2+10 µFOUTPUTVOLTAGE2.5 V3.3 V3.6 V4 V5 V6.4 VR11913093484029750R2169169169169169169UNITkΩkΩkΩkΩkΩkΩTPS7301VI0.1 µF<0.5 VINRESET>2.7 VENOUTCSR = 1 ΩFigure 43. TPS7301 Adjustable LDO Regulator Programmingundervoltage supervisor functionThe RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the eventof an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulatorto detect the undervoltage condition. When that occurs, the RESET output transistor turns on taking the RESETsignal low.On power up, the output voltage tracks the input voltage. The RESET output becomes active (low) as VIapproaches the minimum required for a valid RESET signal (specified at 1.5 V for 25°C and 1.9 V over fullrecommended operating temperature range). When the output voltage reaches the appropriate positive-goinginput threshold (VIT+), a 200-ms (typical) timeout period begins during which the RESET output remains low.Once the timeout has expired, the RESET output becomes inactive. Since the RESET output is an open-drainNMOS, a pullup resistor should be used to ensure that a logic-high signal is indicated.The supply-voltage-supervisor function is also activated during power-down. As the input voltage decays andafter the dropout voltage is reached, the output voltage tracks linearly with the decaying input voltage. Whenthe output voltage drops below the specified negative-going input threshold (VIT– — see electricalcharacteristics tables), the RESET output becomes active (low). It is important to note that if the input voltagedecays below the minimum required for a valid RESET, the RESET is undefined.Since the circuit is monitoring the regulator output voltage, the RESET output can also be triggered by disablingthe regulator or by any fault condition that causes the output to drop below VIT–. Examples of fault conditionsinclude a short circuit on the output and a low input voltage. Once the output voltage is reestablished, either byreenabling the regulator or removing the fault condition, then the internal timer is initiated, which holds theRESET signal active during the 200-ms (typical) timeout period.34POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997APPLICATION INFORMATIONundervoltage supervisor function (continued)Transient loads or line pulses can also cause a reset to occur if proper care is not taken in selecting the inputand output capacitors. Load transients that are faster than 5 µs can cause a reset if high-ESR output capacitors(greater than approximately 7 Ω) are used. A 1-µs transient causes a reset when using an output capacitor withgreater than 3.5 Ω of ESR. Note that the output-voltage spike during the transient can drop well below the resetthreshold and still not trip if the transient duration is short. A 1-µs transient must drop at least 500 mV below thethreshold before tripping the reset circuit. A 2-µs transient trips RESET at just 400 mV below the threshold.Lower-ESR output capacitors help by reducing the drop in output voltage during a transient and should be usedwhen fast transients are expected.NOTE:VIT+ = VIT– +Hysteresisoutput noiseThe TPS73xx has very low output noise, with a spectral noise density < 2 µV/√Hz. This is important whennoise-susceptible systems, such as audio amplifiers, are powered by the regulator.regulator protectionThe TPS73xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when theinput voltage drops below the output voltage (e.g., during power down). Current is conducted from the outputto the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might beappropriate.The TPS73xx also features internal current limiting and thermal protection. During normal operation, theTPS73xx limits output current to approximately 1 A. When current limiting engages, the output voltage scalesback linearly until the overcurrent condition ends. While current limiting is designed to prevent gross devicefailure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature ofthe device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulatoroperation resumes.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•35SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONMECHANICAL DATAD (R-PDSO-G**) 14 PIN SHOWNPINS **DIM0.020 (0,51)0.014 (0,35)148A MIN0.244 (6,20)0.228 (5,80)0.157 (4,00)0.150 (3,81)0.1(4,80)0.337(8,55)0.386(9,80)0.010 (0,25)MA MAX PLASTIC SMALL-OUTLINE PACKAGE0.050 (1,27)80.197(5,00)140.344(8,75)160.394(10,00)0.008 (0,20) NOM1A7Gage Plane0.010 (0,25)0°–ā8°0.044 (1,12)0.016 (0,40)Seating Plane0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)0.004 (0,10)4040047/B 03/95NOTES:A.B.C.D.E.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).Four center pins are connected to die mount pad.Falls within JEDEC MS-01236POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONSLVS124E – JUNE 1995 – REVISED APRIL 1997MECHANICAL DATAP (R-PDIP-T8) 0.400 (10,60)0.355 (9,02)85PLASTIC DUAL-IN-LINE PACKAGE0.260 (6,60)0.240 (6,10)140.070 (1,78) MAX0.020 (0,51) MIN0.310 (7,87)0.290 (7,37)0.200 (5,08) MAXSeating Plane0.125 (3,18) MIN0.100 (2,)0.021 (0,53)0.015 (0,38)0.010 (0,25)M0°–ā15°0.010 (0,25) NOM4040082/B 03/95NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Falls within JEDEC MS-001POST OFFICE BOX 655303 DALLAS, TEXAS 75265•37SLVS124E – JUNE 1995 – REVISED APRIL 1997TPS7301Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350QLOW-DROPOUT VOLTAGE REGULATORSWITH INTEGRATED DELAYED RESET FUNCTIONMECHANICAL DATAPW (R-PDSO-G**) 14 PIN SHOWN0,320,17148 PLASTIC SMALL-OUTLINE PACKAGE0,650,13M0,15 NOM4,504,306,706,10Gage Plane0,251A70°–ā8°0,750,50Seating Plane1,20 MAX0,10 MIN0,10PINS **DIMA MAX83,10145,10165,10206,60247,902,80A MIN2,904,904,906,407,709,6040400/D 10/95NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-15338POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IMPORTANT NOTICE

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