LM20242MH资料

LM20242 36V, 2A PowerWise® Adjustable Frequency Synchronous Buck RegulatorNovember 1, 2007

LM20242

36V, 2A PowerWise® Adjustable Frequency SynchronousBuck Regulator

General Description

The LM20242 is a full featured 1MHz capable synchronousbuck regulator capable of delivering up to 2A of load current.The current mode control loop is externally compensated withonly two external components, offering both high perfor-mance and ease of use. The device is optimized to work overthe input voltage range of 4.5V to 36V making it well suitedfor high voltage systems.

The device features internal Over Voltage Protection (OVP)and Over Current Protection (OCP) circuits for increased sys-tem reliability. A precision Enable pin and integrated UVLOallows the turn on of the device to be tightly controlled andsequenced. Startup inrush currents are limited by both an in-ternally fixed and externally adjustable soft-start circuit. Faultdetection and supply sequencing are possible with the inte-grated PGOOD circuit.

The LM20242 is designed to work well in multi-rail powersupply architectures. The output voltage of the device can beconfigured to track a higher voltage rail using the SS/TRK pin.If the output of the LM20242 is pre-biased at startup it will notsink current to pull the output low until the internal soft-startramp exceeds the voltage at the feedback pin.

The LM20242 is offered in an exposed pad 20 pin TSSOPpackage that can be soldered to the PCB, eliminating theneed for bulky heatsinks.

Features

■■■■■■■■■■■■

2A Output Current, 3.7A peak current

130 mΩ/110 mΩ integrated power MOSFETs1.5% output voltage accuracy

Current Mode Control, selectable compensationResistor programmed, 1MHz capable oscillatorSynchronous rectifier with diode emulationAdjustable output voltage down to 0.8VCompatible with pre-biased loads

Programmable soft-start with external capacitorPrecision enable pin with hysteresisOVP, UVLO inputs and PGOOD output

Internally protected with peak current limit, thermalshutdown and restart

■Accurate current limit with frequency foldback■Non-linear current mode slope compensation■eTSSOP-20 exposed pad package

Applications

■Simple to design, high efficiency point of load regulation

from a 4.5V to 36V bus

■High Performance DSPs, FPGAs, ASICs andMicroprocessors

■Communications Infrastructure, Automotive

Simplified Application Circuit

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PowerWise® is a registered trademark of National Semiconductor Corporation.

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LM20242Connection Diagram

Top View

eTSSOP-20 Package

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Ordering Information

Order NumberLM20242MHLM20242MHELM20242MHX

Package TypeeTSSOP-20

NSC Package Drawing

MXA20A

Package Marking

20242MH

Supplied As73 Units per Rail250 Units per Tape and Reel2500 Units per Tape and Reel

Pin Descriptions

Pin(s)1

NameSS/TRK

Description

Soft-Start or Tracking control input

Application Information

An internal 5 µA current source charges an external capacitor to setthe soft-start rate. The PWM can Track to an external voltage rampwith a low impedance source. If left open, an internal 1 ms SS rampis activated.

This pin is connected to the inverting input of the internal

transconductance error amplifier. An 800 mV reference is internallyconnected to the non-inverting input of the error amplifier.

Open drain output indicating the output voltage is regulating withintolerance. A pull-up resistor of 10 kΩ to 100 kΩ is recommended if thisfunction is used.

2FB

Feedback input to the error amplifierfrom the regulated outputPower good output signal

3PGOOD

45,6,15,167,8,13,14

COMPVINSW

Output of the internal error amplifier andThe loop compensation network should be connected between theinput to the Pulse Width ModulatorCOMP pin and the AGND pin.Input supply voltageSwitch pin

Nominal operating range: 4.5V to 36V.

The drain terminal of the internal Synchronous Rectifier power

NMOSFET and the source terminal of the internal Control powerNMOSFET.

Internal reference for the power MOSFETs.Internal reference for the regulator control functions.

An internal diode from VCC to BOOT charges an external capacitorrequired from SW to BOOT to power the Control MOSFET gate driver.

9,10,11121718

GNDAGNDBOOTVCC

GroundAnalog ground

Boost input for bootstrap capacitor

Output of the high voltage linearVCC tracks VIN up to about 7.2V. Above VIN = 7.2V, VCC is regulatedregulator. The VCC voltage is regulatedto approximately 5.5 Volts. A 0.1 µF to 1 µF ceramic decouplingto approximately 5.5V.capacitor is required. The VCC pin is an output only.Enable or UVLO input

An external voltage divider can be used to set the line undervoltage

lockout threshold. If the EN pin is left unconnected, a 2 µA pull-upcurrent source pulls the EN pin high to enable the regulator.

19EN

20EP

RT

Internal oscillator frequency adjust inputNormally biased at 550 mV. An external resistor connected between

RT and AGND sets the internal oscillator frequency.

Exposed metal pad on the underside of the package with a weakelectrical connection to GND. Connect this pad to the PC board groundplane in order to improve heat dissipation.

2

ExposedExposed padPad

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LM20242Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.VIN to GNDBOOT to GNDBOOT to SWSW to GND

SW to GND (Transient)

FB, EN, SS/TRK, PGOOD toGND

-0.3V to +38V-0.3V to +43V-0.3V to +7V-0.5V to +38V-1.5V (< 20 ns)-0.3V to +6V

VCC to GND

Storage TemperatureESD Rating

Human Body Model (Note 2)-0.3V to +8V-65°C to 150°C

2kV

Operating Ratings

VIN to GND

Junction Temperature

+4.5V to +36V−40°C to + 125°C

Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard

type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimumand Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likelyparametric norm at TJ = 25°C, and are provided for reference purposes only.SymbolVFBRHSW-DS(ON)RLSW-DS(ON)

IQISDVUVLOVUVLO(HYS)

VVCCISSIBOOTVF-BOOTPowergood

VFB(OVP)VFB(OVP-HYS)

VFB(PG)VFB(PG-HYS)TPGOODIPGOOD(SNK)IPGOOD(SRC)Oscillator

FSW1FSW2TOFF-TIME

VRT

Error Amplifier

IFBICOMP(SRC)ICOMP(SNK)

gmAVOLGBW

Feedback pin bias currentCOMP Output Source CurrentCOMP Output Sink Current

Error Amplifier DC TransconductanceError Amplifier Voltage Gain

Error Amplifier Gain-Bandwidth Product

VFB = 1VVFB = 0VVCOMP = 0VVFB = 1V

VCOMP = 0.5V

ICOMP = -50 µA to +50 µACOMP pin openCOMP pin open

200200400

5040035051520007

600

nAµAµAµmhoV/VMHz

Switching Frequency 1Switching Frequency 2Minimum Off TimeRT pin voltage

RRT = 49.9 kΩRRT = 249 kΩ

RRT = 250 kΩ

675225

75025050550

825325

kHzkHznsmV

Over Voltage Protection Rising ThresholdOver Voltage Protection HysteresisPGOOD Rising ThresholdPGOOD HysteresisPGOOD delay

PGOOD Low Sink CurrentPGOOD High Leakage Current

VFB(OVP) / VFBΔVFB(OVP) / VFBVFB(PG) / VFBΔVFB(PG) / VFB

VPGOOD = 0.5VVPGOOD = 5V

107 93 0.6

11029522015

1123973 200

%%%%µsmAnA

Parameter

Feedback pin voltage

High-Side MOSFET On-ResistanceLow-Side MOSFET On-ResistanceOperating Quiescent CurrentShutdown Quiescent currentVIN Under Voltage Lockout

VIN Under Voltage Lockout HysteresisVCC Voltage

Soft-Start Pin Source CurrentBOOT Diode LeakageBOOT Diode Forward Voltage

Conditions

VVIN = 4.5V to 36V

VCOMP = 500 mV to 700 mVISW = 200 mAISW = 200 mAVVIN = 4.5V to 36VVEN = 0VRising VVIN

IVCC = -5 mA, VEN = 5VVSS = 0VVBOOT = 4VIBOOT = -100 mA

Min0.788 3.65 3

Typ0.813011021503.92005.55100.9

Max0.81222519031804.2400 7 1.1

UnitsVmΩmΩmAµAVmVVµAnAV

Electrical Characteristics

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LM20242SymbolCurrent Limit

ILIMTILIM

EnableVEN(RISING)VEN(HYS)

IENTSDTSD(HYS)θJCθJA

Parameter

Cycle By Cycle Current LimitCycle By Cycle Current Limit DelayEN Pin Rising ThresholdEN Pin HysteresisEN Source CurrentThermal Shutdown

Thermal Shutdown HysteresisJunction to CaseJunction to Ambient

Conditions

VEN = 0V, VVIN = 12V

0 LFM airflow

Min3.1 1.2

Typ3.71501.25502170205.630

Max4.65 1.3

UnitsAnsVmVµA°C°C°C/W°C/W

Thermal Shutdown

Thermal Resistance

Note 1:Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for which the device isintended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.Note 2:The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin.

Note 3:Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using StatisticalQuality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Typical Performance Characteristics

Efficiency vs. Load Current

fSW = 350 kHz

Unless otherwise specified: TJ = 25°C, VVIN = 12V

Efficiency vs. Load Current

fSW = 500 kHz

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LM20242Error Amplifier GainError Amplifier Phase

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Line Regulation

VCC vs. VIN

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Non-Switching IQ vs. VINShutdown IQ vs. VIN

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LM20242PGOOD VOL vs. IPGOOD

EN Threshold and Hysteresis vs. Temperature

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EN Current vs. Temperature

Oscillator Frequency vs. RRT

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Oscillator Frequency vs. VIN

High-Side FET Resistance vs. Temperature

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LM20242Load Transient ResponseLow-Side FET Resistance vs. Temperature

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Peak Current Limit vs. Temperature

Startup with CSS = 0

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Startup with CSS = 200 nF

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LM20242Block Diagram

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LM20242Operation Description

GENERAL

The LM20242 switching regulator features all of the functionsnecessary to implement an efficient low voltage buck regula-tor using a minimum number of external components. Thiseasy to use regulator features two integrated switches and iscapable of supplying up to 2A of continuous output current.The regulator utilizes peak current mode control with nonlin-ear slope compensation to optimize stability and transientresponse over the entire output voltage range. Peak currentmode control also provides inherent line feed-forward, cycle-by-cycle current limiting and easy loop compensation. Theswitching frequency can be varied from 100 kHz to 1 MHz withan external resistor to ground. The device can operate at highswitching frequency allowing use of a small inductor while stillachieving efficiencies as high as 93%. The precision internalvoltage reference allows the output to be set as low as 0.8V.Fault protection features include: current limiting, thermalshutdown, over voltage protection, and shutdown capability.The device is available in the eTSSOP-20 package featuringan exposed pad to aid thermal dissipation. The typical appli-cation circuit for the LM20242 is shown in Figure 2 in thedesign guide.

PRECISION ENABLE

The enable (EN) pin allows the output of the device to be en-abled or disabled with an external control signal. This pin is aprecision analog input that enables the device when the volt-age exceeds 1.25V (typical). The EN pin has 50 mV of hys-teresis and will disable the output when the enable voltagefalls below 1.2V (typical). If the EN pin is not used, it shouldbe disconnected so the internal 2 µA pull-up will default thisfunction to the enabled condition. Since the enable pin has aprecise turn-on threshold it can be used along with an externalresistor divider network from VIN to configure the device toturn-on at a precise input voltage. The precision enable cir-cuitry will remain active even when the device is disabled.PEAK CURRENT MODE CONTROL

In most cases, the peak current mode control architectureused in the LM20242 only requires two external componentsto achieve a stable design. The compensation can be select-ed to accommodate any capacitor type or value. The externalcompensation also allows the user to set the crossover fre-quency and optimize the transient performance of the device.For duty cycles above 50% all current mode control buckconverters require the addition of an artificial ramp to avoidsub-harmonic oscillation. This artificial linear ramp is com-monly referred to as slope compensation. What makes theLM20242 unique is the amount of slope compensation willchange depending on the output voltage. When operating athigh output voltages the device will have more slope com-pensation than when operating at lower output voltages. Thisis accomplished in the LM20242 by using a non-linearparabolic ramp for the slope compensation. The parabolicslope compensation of the LM20242 is much better than thetraditional linear slope compensation because it optimizes thestability of the device over the entire output voltage range.CURRENT LIMIT

The precise current limit enables the device to operate withsmaller inductors that have lower saturation currents. Whenthe peak inductor current reaches the current limit threshold,an over current event is triggered and the internal high-sideFET turns off and the low-side FET turns on, allowing the in-ductor current to ramp down until the next switching cycle. For

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each sequential over-current event, the reference voltage isdecremented and PWM pulses are skipped resulting in a cur-rent limit that does not aggressively fold back for brief over-current events, while at the same time providing frequencyand voltage foldback protection during hard short circuit con-ditions.

SOFT-START AND VOLTAGE TRACKING

The SS/TRK pin is a dual function pin that can be used to setthe startup time or track an external voltage source. The start-up or soft-start time can be adjusted by connecting a capacitorfrom the SS/TRK pin to ground. The soft-start feature allowsthe regulator output to gradually reach the steady state oper-ating point, thus reducing stresses on the input supply andcontrolling startup current. If no soft-start capacitor is used thedevice defaults to the internal soft-start circuitry resulting in astartup time of approximately 1 ms. For applications that re-quire a monotonic startup or utilize the PGOOD pin, an ex-ternal soft-start capacitor is recommended. The SS/TRK pincan also be set to track an external voltage source. The track-ing behavior can be adjusted by two external resistors con-nected to the SS/TRK pin as shown in Figure 7. in the designguide.

PRE-BIAS STARTUP CAPABILITY

The LM20242 is in a pre-biased state when it starts up withan output voltage greater than zero. This often occurs in manymulti-rail applications such as when powering an FPGA,ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supplyrail to another. Even though the LM20242 is a synchronousconverter, it will not pull the output low when a pre-bias con-dition exists. During start up the LM20242 will not sink currentuntil the soft-start voltage exceeds the voltage on the FB pin.Since the device cannot sink current, it protects the load fromdamage that might otherwise occur if current is conductedthrough the parasitic paths of the load.

POWER GOOD AND OVER VOLTAGE FAULT HANDLINGThe LM20242 has built in under and over voltage compara-tors that control the power switches. Whenever there is anexcursion in output voltage above the set OVP threshold, thepart will terminate the present on-pulse, turn-on the low-sideFET, and pull the PGOOD pin low. The low-side FET will re-main on until either the FB voltage falls back into regulationor the zero cross detection is triggered which in turn tri-statesthe FETs. If the output reaches the UVP threshold the part willcontinue switching and the PGOOD pin will be deassertedand go low. Typical values for the PGOOD resistor are on theorder of 100 kΩ or less. To avoid false tripping during transientglitches the PGOOD pin has 20 µs of built in deglitch time toboth rising and falling edges.

UVLO

The LM20242 has an internal under-voltage lockout protec-tion circuit that keeps the device from switching until the inputvoltage reaches 3.9V (typical). The UVLO threshold has 200mV of hysteresis that keeps the device from responding topower-on glitches during start up. If desired the turn-on pointof the supply can be changed by using the precision enablepin and a resistor divider network connected to VIN as shownin Figure 6 in the design guide.

THERMAL PROTECTION

Internal thermal shutdown circuitry is provided to protect theintegrated circuit in the event that the maximum junction tem-perature is exceeded. When activated, typically at 170°C, the

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LM20242LM20242 tri-states the power FETs and resets soft-start. Afterthe junction cools to approximately 150°C, the part starts upusing the normal start up routine. This feature is provided toprevent catastrophic failures from accidental device over-heating.

LIGHT LOAD OPERATION

The LM20242 offers increased efficiency when operating atlight loads. Whenever the load current is reduced to a pointwhere the peak to peak inductor ripple current is greater thantwo times the load current, the part will enter the diode emu-lation mode preventing significant negative inductor current.The point at which this occurs is the critical conduction bound-ary and can be calculated by the following equation:

Several diagrams are shown in Figure 1 illustrating continu-ous conduction mode (CCM), discontinuous conductionmode, and the boundary condition.

It can be seen that in diode emulation mode, whenever theinductor current reaches zero the SW node will become highimpedance. Ringing will occur on this pin as a result of the LCtank circuit formed by the inductor and the parasitic capaci-tance. If this ringing is of concern, an additional RC snubbercircuit can be added from the switch node to ground.

At very light loads, usually below 100 mA, several pulses maybe skipped in between switching cycles, effectively reducingthe switching frequency and further improving light-load effi-ciency.

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FIGURE 1. Modes of Operation for LM20242

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LM20242Design Guide

This section walks the designer through the steps necessaryto select the external components to build a fully functionalpower supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design for efficiency, size, or

performance. These will be taken into account and highlight-ed throughout this discussion. To facilitate component selec-tion discussions the circuit shown in Figure 2 below may beused as a reference. Unless otherwise indicated all formulasassume units of amps (A) for current, farads (F) for capaci-tance, henries (H) for inductance and volts (V) for voltages.

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FIGURE 2. Typical Application Circuit

The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETsand parasitic resistances it can be approximated by:

INDUCTOR SELECTION (L)

The inductor value is determined based on the operating fre-quency, load current, ripple current and duty cycle.

The inductor selected should have a saturation current ratinggreater than the peak current limit of the device. Keep in mindthe specified current limit does not account for delay of thecurrent limit comparator, therefore the current limit in the ap-plication may be higher than the specified value. To optimizethe performance and prevent the device from entering currentlimit at maximum load, the inductance is typically selectedsuch that the ripple current, ΔiL, is not greater than 30% of therated output current. Figure 3 illustrates the switch and in-ductor ripple current waveforms. Once the input voltage, out-put voltage, operating frequency and desired ripple currentare known, the minimum value for the inductor can be calcu-lated by the formula shown below:

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FIGURE 3. Switch and Inductor Current WaveformsIf needed, slightly smaller value inductors can be used, how-ever, the peak inductor current, IOUT + ΔiL/2, should be keptbelow the peak current limit of the device. In general, the in-ductor ripple current, ΔiL, should be more than 10% of therated output current to provide adequate current sense infor-mation for the current mode control loop. If the ripple currentin the inductor is too low, the control loop will not have suffi-cient current sense information and can be prone to instability.OUTPUT CAPACITOR SELECTION (COUT)

The output capacitor, COUT, filters the inductor ripple currentand provides a source of charge for transient load conditions.A wide range of output capacitors may be used with theLM20242 that provide excellent performance. The best per-formance is typically obtained using ceramic, SP or OSCONtype chemistries. Typical trade-offs are that the ceramic ca-pacitor provides extremely low ESR to reduce the outputripple voltage and noise spikes, while the SP and OSCONcapacitors provide a large bulk capacitance in a small volumefor transient loading conditions.

When selecting the value for the output capacitor, the twoperformance characteristics to consider are the output volt-age ripple and transient response. The output voltage ripplecan be approximated by using the following formula.

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LM20242TABLE 1. Suggested Values for RFB1 and RFB2

RFB1(kΩ)short

Where, ΔVOUT (V) is the amount of peak to peak voltage rippleat the power supply output, RESR (Ω) is the series resistanceof the output capacitor, fSW(Hz) is the switching frequency,and COUT (F) is the output capacitance used in the design.The amount of output ripple that can be tolerated is applica-tion specific; however a general recommendation is to keepthe output ripple less than 1% of the rated output voltage.Keep in mind ceramic capacitors are sometimes preferredbecause they have very low ESR; however, depending onpackage and voltage rating of the capacitor the value of thecapacitance can drop significantly with applied voltage. Theoutput capacitor selection will also affect the output voltagedroop during a load transient. The peak droop on the outputvoltage during a load transient is dependent on many factors;however, an approximation of the transient droop ignoringloop bandwidth can be obtained using the following equation.

4.998.8712.721.531.6

RFB2(kΩ)open1010.210.210.210.2

VOUT0.81.21.51.82.53.3

If different output voltages are required, RFB2 should be se-lected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can becalculated using the equation below.

ADJUSTING THE OPERATING FREQUENCY (RRT)

The operating frequency of the LM20242 can be adjusted byconnecting a resistor from the RT pin to ground. The equationshown below can be used to calculate the value of RRT for agiven operating frequency.

Where, COUT (F) is the minimum required output capacitance,L (H) is the value of the inductor, VDROOP (V) is the outputvoltage drop ignoring loop bandwidth considerations, ΔIOUT-STEP (A) is the load step change, RESR (Ω) is the outputcapacitor ESR, VIN (V) is the input voltage, and VOUT (V) isthe set regulator output voltage. Both the tolerance and volt-age coefficient of the capacitor should be examined whendesigning for a specific output ripple or transient droop target.INPUT CAPACITOR SELECTION

Good quality input capacitors are necessary to limit the ripplevoltage at the VIN pin while supplying most of the switch cur-rent during the on-time. In general it is recommended to usea ceramic capacitor for the input as they provide both a lowimpedance and small footprint. One important note is to usea good dielectric for the ceramic capacitor such as X5R orX7R. These provide better over temperature performanceand also minimize the DC voltage derating that occurs on Y5Vcapacitors. The input capacitors should be placed as close aspossible to the VIN and GND pins on both sides of the device.Non-ceramic input capacitors should be selected for RMScurrent rating and minimum ripple voltage. A good approxi-mation for the required ripple current rating is given by therelationship:

Where, fSW is the switching frequency in kHz, and RRT is thefrequency adjust resistor in kΩ. Please refer to the curve Os-cillator Frequency versus RRT in the typical performance char-acteristics section. If the RRT resistor is omitted the device willnot operate.

LOOP COMPENSATION (RC1, CC1)

The purpose of loop compensation is to meet static and dy-namic performance requirements while maintaining adequatestability. Optimal loop compensation depends on the outputcapacitor, inductor, load and the device itself.

The overall loop transfer function is the product of the powerstage and the feedback network transfer functions. For sta-bility purposes, the objective is to have a loop gain slope thatis -20db/decade from a very low frequency to beyond thecrossover frequency. Figure 4 shows the transfer functionsfor power stage, feedback/compensation network, and theresulting closed loop system for the LM20242.

As indicated by the RMS ripple current equation, highest re-quirement for RMS current rating occurs at 50% duty cycle.For this case, the RMS ripple current rating of the input ca-pacitor should be greater than half the output current. For bestperformance, low ESR ceramic capacitors should be placedin parallel with higher capacitance capacitors to provide thebest input filtering for the device.

SETTING THE OUTPUT VOLTAGE (RFB1, RFB2)

The resistors RFB1 and RFB2 are selected to set the outputvoltage for the device. Table 1 provides suggestions forRFB1 and RFB2 for common output voltages.

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LM20242A higher crossover frequency can be obtained, usually at theexpense of phase margin, by lowering the value of CC1 andrecalculating the value of RC1. Likewise, increasing CC1 andrecalculating RC1 will provide additional phase margin at alower crossover frequency. As with any attempt to compen-sate the LM20242 the stability of the system should be verifiedfor desired transient droop and settling time.

If the output filter zero, fZ(FIL) approaches the crossover fre-quency (FC), an additional capacitor (CC2) should be placedat the COMP pin to ground. This capacitor adds a pole tocancel the output filter zero assuring the crossover frequencywill occur before the double pole at fSW/2 degrades the phasemargin. The output filter zero is set by the output capacitorvalue and ESR as shown in the equation below.

If needed, the value for CC2 should be calculated using theequation shown below.

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FIGURE 4. LM20242 Loop Compensation

The power stage transfer function is dictated by the modula-tor, output LC filter, and load; while the feedback transferfunction is set by the feedback resistor ratio, error amp gainand external compensation network.

To achieve a -20dB/decade slope, the error amplifier zero,located at fZ(EA), should be positioned to cancel the output fil-ter pole (fP(FIL)). An additional error amp pole, located at fP2(EA), can be added to cancel the output filter zero at fZ(FIL).Cancellation of the output filter zero is recommended if largervalue, non-ceramic output capacitors are used.

Compensation of the LM20242 is achieved by adding an RCnetwork as shown in Figure 5 below.

Where RESR is the output capacitor series resistance andRC1 is the calculated compensation resistance.

BOOT CAPACITOR (CBOOT)

The LM20242 integrates an N-Channel buck switch and as-sociated floating high voltage level shift / gate driver. This gatedriver circuit works in conjunction with an internal diode andan external bootstrap capacitor. A 0.1 µF ceramic capacitor,connected with short traces between the BOOT pin and SWpin, is recommended. During the off-time of the buck switch,the SW pin voltage is approximately 0V and the bootstrap ca-pacitor is charged from VCC through the internal bootstrapdiode.

SUB-REGULATOR BYPASS CAPACITOR (CVCC)

The capacitor at the VCC pin provides noise filtering for theinternal sub-regulator. The recommended value of CVCCshould be no smaller than 0.1 µF and no greater than 1 µF.The capacitor should be a good quality ceramic X5R or X7Rcapacitor. In general, a 1 µF ceramic capacitor is recom-mended for most applications. The VCC regulator should notbe used for other functions since it isn't protected againstshort circuit.

SETTING THE START UP TIME (CSS)

The addition of a capacitor connected from the SS pin toground sets the time at which the output voltage will reach thefinal regulated value. Larger values for CSS will result in longerstart up times. Table 3, shown below provides a list of softstart capacitors and the corresponding typical start up times.

TABLE 2. Start Up Times for Different Soft-Start

CapacitorsStart Up Time (ms)

15101520

13

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FIGURE 5. Compensation Network for LM20242A good starting value for CC1 for most applications is 4.7 nF.Once the value of CC1 is chosen the value of RC should becalculated using the equation below to cancel the output filterpole (fP(FIL)) as shown in Figure 4.

CSS (nF)none3368100120

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LM20242If different start up times are needed the equation shown be-low can be used to calculate the start up time.

TRACKING AN EXTERNAL SUPPLY

By using a properly chosen resistor divider network connect-ed to the SS/TRK pin, as shown in Figure 7, the output of theLM20242 can be configured to track an external voltagesource to obtain a simultaneous or ratiometric start up.

As shown above, the start up time is influenced by the valueof the soft-start capacitor CSS(F) and the 5 µA soft-start pincurrent ISS(A). that may be found in the electrical character-istics table.

While the soft-start capacitor can be sized to meet many startup requirements, there are limitations to its size. The soft-starttime can never be faster than 1 ms due to the internal default1 ms start up time. When the device is enabled there is anapproximate time interval of 50 µs when the soft-start capac-itor will be discharged just prior to the soft-start ramp. If theenable pin is rapidly pulsed or the soft-start capacitor is largethere may not be enough time for CSS to completely dischargeresulting in start up times less than predicted. To aid in dis-charging of soft-start capacitor during long disable periods anexternal 1MΩ resistor from SS/TRK to ground can be usedwithout greatly affecting the start up time.

USING PRECISION ENABLE AND POWER GOOD

The precision enable (EN) and power good (PGOOD) pins ofthe LM20242 can be used to address many sequencing re-quirements. The turn-on of the LM20242 can be controlledwith the precision enable pin by using two external resistorsas shown in Figure 6 .

30031461

FIGURE 7. Tracking an External Supply

Since the soft-start charging current ISS is always present onthe SS/TRK pin, the size of R2 should be less than 10 kΩ tominimize the errors in the tracking output. Once a value forR2 is selected the value for R1 can be calculated using ap-propriate equation in Figure 8, to give the desired start up.Figure 8 shows two common start up sequences; the topwaveform shows a simultaneous start up while the waveformat the bottom illustrates a ratiometric start up.

30031462

FIGURE 6. Sequencing LM20242 with Precision EnableThe value for resistor RB can be selected by the user to controlthe current through the divider. Typically this resistor will beselected to be between 10 kΩ and 1 MΩ. Once the value forRB is chosen the resistor RA can be solved using the equationbelow to set the desired turn-on voltage.

When designing for a specific turn-on threshold (VTO) the tol-erance on the input supply, enable threshold (VIH_EN), andexternal resistors need to be considered to insure proper turn-on of the device.

The LM20242 features an open drain power good (PGOOD)pin to sequence external supplies or loads and to provide faultdetection. This pin requires an external resistor (RPG) to pullPGOOD high when the output is within the PGOOD tolerancewindow. Typical values for this resistor range from 10 kΩ to100 kΩ.

30031478

FIGURE 8. Common Start Up Sequences

A simultaneous start up is preferred when powering most FP-GAs, DSPs, or other microprocessors. In these systems thehigher voltage, VOUT1, usually powers the I/O, and the lowervoltage, VOUT2, powers the core. A simultaneous start up pro-vides a more robust power up for these applications since itavoids turning on any parasitic conduction paths that may ex-ist between the core and the I/O pins of the processor.

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LM20242The second most common power on behavior is known as aratiometric start up. This start up is preferred in applicationswhere both supplies need to be at the final value at the sametime.

Similar to the soft-start function, the fastest start up possibleis 1ms regardless of the rise time of the tracking voltage.When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide sufficient overdriveand transient immunity.

BENEFIT OF AN EXTERNAL SCHOTTKY

During dead time, the body diode of the synchronous MOS-FET acts as a free-wheeling diode and conducts the inductorcurrent. The MOSFET is optimized for high breakdown volt-age, but this makes an inefficient body diode reverse recoverycharge. The power loss is proportional to load current andswitching frequency. The loss increases at higher input volt-ages and switching frequencies. One simple solution is to usea small 1A external Schottky diode between SW and GND asshown in Figure 10, diodes D1 and D2. The external Schottkydiode effectively conducts all inductor current during the deadtime, minimizing the current passing through the synchronousMOSFET body diode and eliminating reverse recovery loss-es.

The external Schottky conducts currents for a very small por-tion of the switching cycle, therefore the average current islow. An external Schottky rated for 1A will improve efficiencyby several percent in some applications. A Schottky rated ata higher current will not significantly improve efficiency andmay be worse due to the increased reverse capacitance. Theforward voltage of the synchronous MOSFET body diode isapproximately 700 mV, therefore an external Schottky with aforward voltage less than or equal to 700 mV should be se-lected to ensure the majority of the dead time current is carriedby the Schottky.

THERMAL CONSIDERATIONS

The thermal characteristics of the LM20242 are specified us-ing the parameter θJA, which relates the junction temperatureto the ambient temperature. Although the value of θJA is de-pendant on many variables, it still can be used to approximatethe operating junction temperature of the device.

To obtain an estimate of the device junction temperature, onemay use the following relationship:

TJ = PD x θJA + TA

and

PD = PIN x (1 - Efficiency) - 1.1 x (IOUT)2 x DCR

Where:

TJ is the junction temperature in °C.

PIN is the input power in Watts (PIN = VIN x IIN).

θJA is the junction to ambient thermal resistance for theLM20242.

TA is the ambient temperature in °C.IOUT is the output load current.

DCR is the inductor series resistance.

It is important to always keep the operating junction temper-ature (TJ) below 125°C for reliable operation. If the junctiontemperature exceeds 160°C the device will cycle in and out

of thermal shutdown. If thermal shutdown occurs it is a signof inadequate heatsinking or excessive power dissipation inthe device.

PCB LAYOUT CONSIDERATIONS

PC board layout is an important part of DC-DC converter de-sign. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI,ground bounce, and resistive voltage loss in the traces. Thesecan send erroneous signals to the DC-DC converter resultingin poor regulation or instability.

Good layout can be implemented by following a few simpledesign rules.

1. Minimize area of switched current loops. In a buck regulatorthere are two loops where currents are switched very fast. Thefirst loop starts from the input capacitor, to the regulator VINpin, to the regulator SW pin, to the inductor then out to theoutput capacitor and load. The second loop starts from theoutput capacitor ground, to the regulator GND pins, to the in-ductor and then out to the load (see Figure 9). To minimizeboth loop areas the input capacitor should be placed as closeas possible to the VIN pin. Grounding for both the input andoutput capacitor should consist of a small localized top sideplane that connects to GND and the exposed pad (EP). Theinductor should be placed as close as possible to the SW pinand output capacitor.

2. Minimize the copper area of the switch node. Since theLM20242 has the SW pins on opposite sides of the packageit is recommended that the SW pins should be connected witha trace that runs around the package. The inductor should beplaced at an equal distance from the SW pins using 100 milwide traces to minimize capacitive and conductive losses.3. Have a single point ground for all device grounds locatedunder the EP. The ground connections for the compensation,feedback, and soft-start components should be connectedtogether then routed to the EP pin of the device. The AGNDpin should connect to GND under the EP. If not properly han-dled poor grounding can result in degraded load regulation orerratic switching behavior.

4. Minimize trace length to the FB pin. Since the feedbacknode can be high impedance the trace from the output resistordivider to FB pin should be as short as possible. This is mostimportant when high value resistors are used to set the outputvoltage. The feedback trace should be routed away from theSW pin and inductor to avoid contaminating the feedback sig-nal with switch noise.

5. Make input and output bus connections as wide as possi-ble. This reduces any voltage drops on the input or output ofthe converter and can improve efficiency. Voltage accuracyat the load is important so make sure feedback voltage senseis made at the load. Doing so will correct for voltage drops atthe load and provide the best output accuracy.

6. Provide adequate device heatsinking. Use as many vias asis possible to connect the EP to the power plane heatsink. Forbest results use a 5x3 via array with a minimum via diameterof 12 mils. \"Via tenting\" with the solder mask may be neces-sary to prevent wicking of the solder paste applied to the EP.See the Thermal Considerations section to insure enoughcopper heatsinking area is used to keep the junction temper-ature below 125°C.

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LM2024230031446

FIGURE 9. Schematic of LM20242 Highlighting Layout Sensitive Nodes

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LM2024230031444

FIGURE 10. Typical Application Schematic

Bill of Materials

IDU1L1C1-3C4, 6, 9C5, 11C7C8C10D1, D2R1,9R2R3R4, 7R5R6R8

Qty1133211122112111

Part NumberLM20242MHMSS1260-153MXGRM32ER71H475KA88L

VJ0805JY104KXXVJ0805Y105JXACW1BCC1608COG1H121JVJ0805Y222JC1210C107M9PAC

MBR00CRCW06031002FCRCW08052053FCRCW08051212FCRCW060330000ZOEACRCW08053212FCRCW08051022FCRCW080992F

SizeeTSSOP-20MSS1260121008050805060308051210SOD1230603080508050603080508050603

DescriptionIC, Switching Regulator15 µH, 4.6A ISAT4.7 µF, 50V, X7R

0.1 µF1 µF120 pF2.2 nF100 µF0.5A, 40V, Schottky

10 kΩ205 kΩ12.1 kΩ0 kΩ32.1 kΩ10.2 kΩ49.9 kΩ

VendorNSCCoilcraftMurataVishayVishayTDKVishayKemetFairchildVishayVishayVishayVishayVishayVishayVishay

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LM20242Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead eTSSOP PackageNS Package Number MXA20A

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LM20242Notes

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LM20242 36V, 2A PowerWise® Adjustable Frequency Synchronous Buck RegulatorNotes

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